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| 101 innovation drive san jose, ca 95134 www.altera.com aiigx5v3-4.3 volume 3: device datasheet and addendum arria ii device handbook document publication date: july 2012 arria ii device handbook volume 3: device datasheet and addendum
arria ii device handbook volume 3: device datasheet and addendum july 2012 altera corporation ? 2012 altera corporation. all rights reserved. altera, arria, cyclone, hardcopy, max, megaco re, nios, quartus and stratix are reg. u.s. pat. & tm. off. and/or trademarks of altera corporation in the u.s. and other countries. all other trademarks and service marks are the property of their respective holders as described at www.altera.com/common/legal.html . altera warrants performance of its semiconductor products to current specifications in accordance with altera?s standard warranty, but reserv es the right to make changes to any products and services at any time without notice . altera assumes no responsibility or liability arising out of the application or us e of any information, product, or servic e described herein except as expressly ag reed to in writing by altera. altera customers are advised to obtain the latest version of device spec ifications before re lying on any published information and bef ore placing orders for products or services. july 2012 altera corporation arria ii device han dbook volume 3: device datasheet and addendum contents chapter revision dates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v section i. device datasheet and a ddendum for arria ii devices revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?1 chapter 1. device datasheet for arria ii devices electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?1 maximum allowed i/o operating frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?4 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?5 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?7 schmitt trigger input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?14 i/o standard specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?15 power consumption for the arria ii device family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?20 switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?21 transceiver performance specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?21 core performance specifications for the arria ii device family . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?53 clock tree specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?53 pll specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?53 dsp block specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?57 embedded memory block specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?58 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?60 jtag specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?60 chip-wide reset (dev_clrn) specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?60 periphery performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?61 high-speed i/o specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?61 external memory interface specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?68 duty cycle distortion (dcd) specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?71 ioe programmable delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?72 i/o timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?73 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?74 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?77 chapter 2. addendum for the arria ii device handbook highlights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?1 high-speed lvds i/o with dpa and soft cdr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?1 auto-calibrating external memory interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?1 connecting a serial configuration device to an arria ii device family on as interface . . . . . . . . . . . 2?1 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?1 additional information how to contact altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . info?1 typographic conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . info?1 iv contents arria ii device handbook volume 3: device datasheet and addendum july 2012 altera corporation july 2012 altera corporation arria ii device han dbook volume 3: device datasheet and addendum chapter revision dates the chapters in this document, arria ii device handbook volume 3: device datasheet and addendum, were revised on the following dates. where chapters or groups of chapters are available separately, part numbers are listed. chapter 1. device datasheet for arria ii devices revised: july 2012 part number: aiigx53001-4.3 chapter 2. addendum for the arria ii device handbook revised: december 2010 part number: aiigx53002-2.0 vi chapter revision dates arria ii device handbook volume 3: device datasheet and addendum july 2012 altera corporation july 2012 altera corporation arria ii device han dbook volume 3: device datasheet and addendum section i. device datasheet and addendum for ar ria ii devices this section provides information about the arria ? ii device family datasheet and addendum. this section includes the following chapters: chapter 1, device datasheet for arria ii devices chapter 2, addendum for the arria ii device handbook revision history refer to each chapter for its own specific revision history. for information on when each chapter was updated, refer to the chapter revision dates section, which appears in this volume. i?2 section i: device datasheet and addendum for arria ii devices revision history arria ii device handbook volume 3: device datasheet and addendum july 2012 altera corporation arria ii device handbook volume 3: device datasheet and addendum july 2012 aiigx53001-4.3 subscribe ? 2012 altera corporation. all rights reserved. altera, arria, cy clone, hardcopy, max, megacore , nios, quartus and stratix are reg. u.s. pat. & tm. off. and/or trademarks of altera corporation in the u.s. and other countries. all other trademarks and service marks are the propert y of their respective holders as described at www.altera.com/common/legal.html . altera warrants performance of its semiconductor products to cu rrent specifications in accordan ce with altera?s standard warr anty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability arising out of th e application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. alte ra customers are advi sed to obtain the latest version of device specifications before relying on any published information and before placi ng orders for products or services. 1. device datasheet for arria ii devices this chapter describes the electrical an d switching characteristics of the arria ? ii device family. the arria ii device family includes the arria ii gx and gz devices. electrical characteristics include operating conditions and power consumption. switching characteristics include transceiver specifications, core, and periphery performance. this chapter also describe s i/o timing, including programmable i/o element (ioe) delay and progra mmable output buffer delay. f for information regarding the densities and packages of devices in the arria ii device family, refer to overview for the arria ii device family chapter. this chapter contains the following sections: ?electrical characteristics? on page 1?1 ?transceiver performance specifications? on page 1?21 ?glossary? on page 1?74 electrical characteristics the following sections describe the electrical characteristics. operating conditions arria ii devices are rated according to a set of defined parameters. to maintain the highest possible performance and reliability of arria ii devices, you must consider the operating requirements described in this chapter. arria ii devices are offered in both comme rcial and industrial grades. arria ii gx devices are offered in ?4 (fastest), ?5, and ?6 (slowest) commercial speed grades and ?3 and ?5 industrial speed grades. arria ii gz devices are offered in ?3 and ?4 speed grades for both commercial and industrial grades. 1 in this chapter, a prefix associated with th e operating temperature range is attached to the speed grades; commercial with the "c" pr efix and industrial with the ?i? prefix. commercial devices are indicated as c4, c5, and c6 speed grade, and the industrial devices are indicated as i3 and i5. absolute maximum ratings absolute maximum ratings define the ma ximum operating conditions for arria ii devices. the values are based on experiments conducted with the device and theoretical modeling of breakdown and damage mechanisms. the functional operation of the device is not implied under these conditions. table 1?1 lists the absolute maximum ratings for arria ii gx devices. table 1?2 lists the absolute maximum ratings for arria ii gz devices. july 2012 aiigx53001-4.3 1?2 chapter 1: device datasheet for arria ii devices electrical characteristics arria ii device handbook volume 3: device datasheet and addendum july 2012 altera corporation c conditions beyond those listed in table 1?1 and table 1?2 may cause permanent damage to the device. additionally, device operation at the absolute maximum ratings for extended periods of time ma y have adverse effects on the device. table 1?1 lists the absolute maximum ratings for arria ii gx devices. table 1?2 lists the absolute maximum ratings for arria ii gz devices. table 1?1. absolute maximum ratings for arria ii gx devices symbol description minimum maximum unit v cc supplies power to the core, periphery, i/o registers, pci express ? (pipe) (pcie) hip block, and transceiver pcs ?0.5 1.35 v v cccb supplies power for the configuration ram bits ?0.5 1.8 v v ccbat battery back-up power supply for design security volatile key register ?0.5 3.75 v v ccpd supplies power to the i/o pre-drivers, differential input buffers, and msel circuitry ?0.5 3.75 v v ccio supplies power to the i/o banks ?0.5 3.9 v v ccd_pll supplies power to the digital portions of the pll ?0.5 1.35 v v cca_pll supplies power to the analog portions of the pll and device-wide power management circuitry ?0.5 3.75 v v i dc input voltage ?0.5 4.0 v i out dc output current, per pin ?25 40 ma v cca supplies power to the transceiver pma regulator ? 3.75 v v ccl_gxb supplies power to the transceiver pma tx, pma rx, and clocking ? 1.21 v v cch_gxb supplies power to the transceiver pma output (tx) buffer ? 1.8 v t j operating junction temperature ?55 125 c t stg storage temperature (no bias) ?65 150 c table 1?2. absolute maximum ratings for arria ii gz devices (part 1 of 2) symbol description minimum maximum unit v cc supplies power to the core, periphery, i/o registers, pcie hip block, and transceiver pcs -0.5 1.35 v v cccb power supply to the configuration ram bits -0.5 1.8 v v ccpgm supplies power to the configuration pins -0.5 3.75 v v ccaux auxiliary supply -0.5 3.75 v v ccbat supplies battery back-up power for design security volatile key register -0.5 3.75 v v ccpd supplies power to the i/o pre-drivers, differential input buffers, and msel circuitry -0.5 3.75 v v ccio supplies power to the i/o banks -0.5 3.9 v v cc_clkin supplies power to the differential clock input -0.5 3.75 v v ccd_pll supplies power to the digital portions of the pll -0.5 1.35 v v cca_pll supplies power to the analog portions of the pll and device-wide power management circuitry -0.5 3.75 v v i dc input voltage -0.5 4.0 v i out dc output current, per pin -25 40 ma chapter 1: device datasheet for arria ii devices 1?3 electrical characteristics july 2012 altera corporation arria ii device han dbook volume 3: device datasheet and addendum maximum allowed overshoot and undershoot voltage during transitions, input signals may overshoot to the voltage shown in table 1?3 and undershoot to ?2.0 v for magnitude of curr ents less than 100 ma and periods shorter than 20 ns. table 1?3 lists the arria ii gx and gz maximu m allowed input overshoot voltage and the duration of the overshoot voltage as a percentage over the device lifetime. the maximum allowed overshoot duration is specified as a percentage of high-time over the lifetime of the device. a dc signal is eq uivalent to 100% duty cycle. for example, a signal that overshoots to 4.3 v can only be at 4.3 v for 5.41% over the lifetime of the device; for a device lifetime of 10 year s, this amounts to 5.41/10ths of a year. v cca_l supplies transceiver high voltage power (left side) -0.5 3.75 v v cca_r supplies transceiver high voltage power (right side) -0.5 3.75 v v cchip_l supplies transceiver hip digital power (left side) -0.5 1.35 v v ccr_l supplies receiver power (left side) -0.5 1.35 v v ccr_r supplies receiver power (right side) -0.5 1.35 v v cct_l supplies transmitter power (left side) -0.5 1.35 v v cct_r supplies transmitter power (right side) -0.5 1.35 v v ccl_gxbln (1) supplies power to the transceiver pma tx, pma rx, and clocking (left side) -0.5 1.35 v v ccl_gxbrn (1) supplies power to the transceiver pma tx, pma rx, and clocking (right side) -0.5 1.35 v v cch_gxbln (1) supplies power to the transceiver pma output (tx) buffer (left side) -0.5 1.8 v v cch_gxbrn (1) supplies power to the transceiver pma output (tx) buffer (right side) -0.5 1.8 v t j operating junction temperature -55 125 c t stg storage temperature (no bias) -65 150 c note to table 1?2 : (1) n = 0, 1, or 2. table 1?2. absolute maximum ratings for arria ii gz devices (part 2 of 2) symbol description minimum maximum unit 1?4 chapter 1: device datasheet for arria ii devices electrical characteristics arria ii device handbook volume 3: device datasheet and addendum july 2012 altera corporation maximum allowed i/o operating frequency table 1?4 lists the maximum allowed i/o operating frequency for arria ii gx i/os using the specified i/o standards to ensure device reliability. table 1?3. maximum allowed overshoot during transitions for arria ii devices symbol description condition (v) overshoot duration as % of high time unit v i (ac) ac input voltage 4.0 100.000 % 4.05 79.330 % 4.1 46.270 % 4.15 27.030 % 4.2 15.800 % 4.25 9.240 % 4.3 5.410 % 4.35 3.160 % 4.4 1.850 % 4.45 1.080 % 4.5 0.630 % 4.55 0.370 % 4.6 0.220 % table 1?4. maximum allowed i/o operating frequency for arria ii gx devices i/o standard i/o frequency (mhz) hstl-18 and hstl-15 333 sstl -15 400 sstl-18 333 2.5-v lvcmos 260 3.3-v and 3.0-v lvttl 250 3.3-v, 3.0-v, 1.8-v, and 1.5-v lvcmos pci and pci-x sstl-2 1.2-v lvcmos hstl-12 200 chapter 1: device datasheet for arria ii devices 1?5 electrical characteristics july 2012 altera corporation arria ii device han dbook volume 3: device datasheet and addendum recommended operating conditions this section lists the functional operation limits for ac and dc parameters for arria ii gx and gz devices. all supplies are required to monotonically reach their full-rail values without plateaus within t ramp . table 1?5 lists the recommended operating conditions for arria ii gx devices. table 1?5. recommended operating conditions for arria ii gx devices (note 1) (part 1 of 2) symbol description condition minimum typical maximum unit v cc supplies power to the core, periphery, i/o registers, pcie hip block, and transceiver pcs ? 0.87 0.90 0.93 v v cccb supplies power to the configuration ram bits ? 1.425 1.50 1.575 v v ccbat (2) battery back-up power supply for design security volatile key registers ? 1.2 ? 3.3 v v ccpd (3) supplies power to th e i/o pre-drivers, differential input buffers, and msel circuitry ? 3.135 3.3 3.465 v ? 2.85 3.0 3.15 v ? 2.375 2.5 2.625 v v ccio supplies power to the i/o banks (4) ? 3.135 3.3 3.465 v ? 2.85 3.0 3.15 v ? 2.375 2.5 2.625 v ? 1.71 1.8 1.89 v ? 1.425 1.5 1.575 v ? 1.14 1.2 1.26 v v ccd_pll supplies power to the digital portions of the pll ? 0.87 0.90 0.93 v v cca_pll supplies power to the analog portions of the pll and device-wide power management circuitry ? 2.375 2.5 2.625 v v i dc input voltage ? ?0.5 ? 3.6 v v o output voltage ? 0 ? v ccio v v cca supplies power to the transceiver pma regulator ? 2.375 2.5 2.625 v v ccl_gxb supplies power to the transceiver pma tx, pma rx, and clocking ? 1.045 1.1 1.155 v v cch_gxb supplies power to the transceiver pma output (tx) buffer ? 1.425 1.5 1.575 v t j operating junction temperature commercial 0 ? 85 c industrial ?40 ? 100 c 1?6 chapter 1: device datasheet for arria ii devices electrical characteristics arria ii device handbook volume 3: device datasheet and addendum july 2012 altera corporation table 1?6 lists the recommended operating conditions for arria ii gz devices. t ramp power supply ramp time normal por 0.05 ? 100 ms fast por 0.05 ? 4 ms notes to table 1?5 : (1) for more information about su pply pin connections, refer to the arria ii device family pi n connection guidelines . (2) altera recommends a 3.0-v nominal battery voltage when connecting v ccbat to a battery for volatile key back up. if you do not use the volatile security key, you may connect the v ccbat to either gnd or a 3.0-v power supply. (3) v ccpd must be 2.5-v for i/o banks with 2.5-v and lower v ccio , 3.0-v for 3.0-v v ccio , and 3.3-v for 3.3-v v ccio . (4) v ccio for 3c and 8c i/o banks where the conf iguration pins reside only supports 3.3-, 3.0-, 2.5-, or 1.8-v voltage levels. table 1?5. recommended operating conditions for arria ii gx devices (note 1) (part 2 of 2) symbol description condition minimum typical maximum unit table 1?6. recommended operating conditions for arria ii gz devices (note 6) (part 1 of 2) symbol description condition minimum typical maximum unit v cc core voltage and periphery circuitry power supply ? 0.87 0.90 0.93 v v cccb supplies power for the configuration ram bits ? 1.45 1.50 1.55 v v ccaux auxiliary supply ? 2.375 2.5 2.625 v v ccpd (2) i/o pre-driver (3.0 v) power supply ? 2.85 3.0 3.15 v i/o pre-driver (2.5 v) power supply ? 2.375 2.5 2.625 v v ccio i/o buffers (3.0 v) power supply ? 2.85 3.0 3.15 v i/o buffers (2.5 v) power supply ? 2.375 2.5 2.625 v i/o buffers (1.8 v) power supply ? 1.71 1.8 1.89 v i/o buffers (1.5 v) power supply ? 1.425 1.5 1.575 v i/o buffers (1.2 v) power supply ? 1.14 1.2 1.26 v v ccpgm configuration pins (3.0 v) power supply ? 2.85 3.0 3.15 v configuration pins (2.5 v) power supply ? 2.375 2.5 2.625 v configuration pins (1.8 v) power supply ? 1.71 1.8 1.89 v v cca_pll pll analog voltage regulator power supply ? 2.375 2.5 2.625 v v ccd_pll pll digital voltage regulator power supply ? 0.87 0.90 0.93 v v cc_clkin differential clock input power supply ? 2.375 2.5 2.625 v v ccbat (1) battery back-up power supply (for design security volatile key register) ? 1.2?3.3v v i dc input voltage ? ?0.5 ? 3.6 v v o output voltage ? 0 ? v ccio v v cca_l transceiver high voltage power (left side) ? 2.85/2.375 3.0/2.5 (4) 3.15/2.625 v v cca_r transceiver high voltage power (right side) ? v cchip_l transceiver hip digital power (left side) ? 0.87 0.9 0.93 v v ccr_l receiver power (left side) ? 1.05 1.1 1.15 v v ccr_r receiver power (right side) ? 1.05 1.1 1.15 v v cct_l transmitter power (left side) ? 1.05 1.1 1.15 v v cct_r transmitter power (right side) ? 1.05 1.1 1.15 v chapter 1: device datasheet for arria ii devices 1?7 electrical characteristics july 2012 altera corporation arria ii device han dbook volume 3: device datasheet and addendum dc characteristics this section lists the supply current, i/ o pin leakage current, on-chip termination (oct) accuracy and variation, input pin capacitance, internal weak pull-up and pull-down resistance, hot socketing, and schmitt trigger input specifications. supply current standby current is the current the device draw s after the device is configured with no inputs or outputs toggling and no activity in the device. because these currents vary largely with the resources used, use the mi crosoft excel-based early power estimator (epe) to get supply current estimates for your design. f for more information about power estimation tools, refer to the powerplay early power estimator user guide and the powerplay power analysis chapter. v ccl_gxbln (3) transceiver clock power (left side) ? 1.05 1.1 1.15 v v ccl_gxbrn (3) transceiver clock power (right side) ? 1.05 1.1 1.15 v v cch_gxbln (3) transmitter output buffer power (left side) ? 1.33/1.425 1.4/1.5 (5) 1.575 v v cch_gxbrn (3) transmitter output buffer power (right side) ? t j operating junction temperature commercial 0 ? 85 c industrial ?40 ? 100 c t ramp power supply ramp time normal por (porsel=0) 0.05 ? 100 ms fast por (porsel=1) 0.05 ? 4 ms notes to table 1?6 : (1) altera recommends a 3.0-v nominal battery voltage when connecting v ccbat to a battery for volatile key backu p. if you do not use the volatile security key, you may connect the v ccbat to either gnd or a 3.0-v power supply. (2) v ccpd must be 2.5 v when v ccio is 2.5, 1.8, 1.5, or 1.2 v. v ccpd must be 3.0 v when v ccio is 3.0 v. (3) n = 0, 1, or 2. (4) v cca_l/r must be connected to a 3.0-v supply if th e clock multiplier unit (cmu ) phase-locked loop (pll), re ceiver clock data recovery ( cdr), or both, are configured at a base data rate > 4.25 gbps . for data rates up to 4.25 gbps, you can connect v cca_l/r to either 3.0 v or 2.5 v. (5) v cch_gxbl/r must be connected to a 1.4-v supply if the transmitter channel data rate is > 6.5 gbps. for data rates up to 6.5 gbps, you can connect v cch_gxbl/r to either 1.4 v or 1.5 v. (6) transceiver power supplies do not have power-on-reset (por) circuitry. after initial power-up, violat ing the transceiver pow er supply operating conditions could lead to unpredictable link behavior. table 1?6. recommended operating conditions for arria ii gz devices (note 6) (part 2 of 2) symbol description condition minimum typical maximum unit 1?8 chapter 1: device datasheet for arria ii devices electrical characteristics arria ii device handbook volume 3: device datasheet and addendum july 2012 altera corporation i/o pin leakage current table 1?7 lists the arria ii gx i/o pin leakage current specifications. table 1?8 lists the arria ii gz i/o pin leakage current specifications. bus hold bus hold retains the last valid logic state af ter the source driving it either enters the high impedance state or is removed. each i/o pin has an option to enable bus hold in user mode. bus hold is always disabled in configuration mode. table 1?9 lists bus hold specifications for arria ii gx devices. table 1?7. i/o pin leakage current for arria ii gx devices symbol description conditions min typ max unit i i input pin v i = 0 v to v cciomax ?10 ? 10 a i oz tri-stated i/o pin v o = 0 v to v cciomax ?10 ? 10 a table 1?8. i/o pin leakage current for arria ii gz devices symbol description conditions min typ max unit i i input pin v i = 0 v to v cciomax ?20 ? 20 a i oz tri-stated i/o pin v o = 0 v to v cciomax ?20 ? 20 a table 1?9. bus hold parameters for arria ii gx devices (note 1) parameter symbol cond. v ccio (v) unit 1.2 1.5 1.8 2.5 3.0 3.3 min max min max min max min max min max min max bus-hold low, sustaining current i susl v in > v il (max.) 8 ?12?30?50?70?70?a bus-hold high, sustaining current i sush v in < v il (min.) ?8 ? ?12 ? ?30 ? ?50 ? ?70 ? ?70 ? a bus-hold low, overdrive current i odl 0v 1?10 chapter 1: device datasheet for arria ii devices electrical characteristics arria ii device handbook volume 3: device datasheet and addendum july 2012 altera corporation table 1?12 lists the oct termination calibration accuracy specifications for arria ii gz devices. 50- ? r s 3.0, 2.5, 1.8, 1.5, 1.2 50- ? series oct with calibration v ccio = 3.0, 2.5, 1.8, 1.5, 1.2 10 10 % 100- ? r d 2.5 100- ? differential oct without calibration v ccio = 2.5 30 30 % note to table 1?11 : (1) oct with calibration accuracy is vali d at the time of calibration only. table 1?11. oct with and without calibration specification for arria ii gx device i/os (note 1) (part 2 of 2) symbol description conditions (v) calibration accuracy unit commercial industrial table 1?12. oct with calibration accuracy specifications for arria ii gz devices (note 1) symbol description conditions (v) calibration accuracy unit c2 c3,i3 c4,i4 25- ? r s 3.0, 2.5, 1.8, 1.5, 1.2 (2) 25- ? series oct with calibration v ccio = 3.0, 2.5, 1.8, 1.5, 1.2 8 8 8 % 50- ? r s 3.0, 2.5, 1.8, 1.5, 1.2 50- ?? internal series oct with calibration v ccio = 3.0, 2.5, 1.8, 1.5, 1.2 8 8 8 % 50- ? r t 2.5, 1.8, 1.5, 1.2 50- ? internal parallel oct with calibration v ccio = 2.5, 1.8, 1.5, 1.2 10 10 10 % 20- ? , 40- ? , and 60- ? r s 3.0, 2.5, 1.8, 1.5, 1.2 (3) 20- ? , 40- ?? and 60- ? r s expanded range for internal series oct with calibration v ccio = 3.0, 2.5, 1.8, 1.5, 1.2 10 10 10 % 25- ? r s_left_shif t 3.0, 2.5, 1.8, 1.5, 1.2 25- ? r s_left_shift internal left shift series oct with calibration v ccio = 3.0, 2.5, 1.8, 1.5, 1.2 10 10 10 % notes to table 1?12 : (1) oct calibration accuracy is valid at the time of calibration only. (2) 25- ? r s is not supported for 1.5 v and 1.2 v in row i/o. (3) 20- ? r s is not supported for 1.5 v and 1.2 v in row i/o. chapter 1: device datasheet for arria ii devices 1?11 electrical characteristics july 2012 altera corporation arria ii device han dbook volume 3: device datasheet and addendum the calibration accuracy for ca librated series and parallel octs are applicable at the moment of calibration. when process, vo ltage, and temperature (pvt) conditions change after calibration, the tolerance may change. table 1?13 lists the arria ii gz oct without cali bration resistance tolerance to pvt changes. oct calibration is automatically performed at power up for oct-enabled i/os. when voltage and temperature conditions change after calibration, the resistance may change. use equation 1?1 and table 1?14 to determine the oct variation when voltage and temperature vary after power-up calibration for arria ii gx and gz devices. table 1?13. oct without calibration resistance tolerance specifications for arria ii gz devices symbol description conditions (v) resistance tolerance unit c3,i3 c4,i4 25- ? r s 3.0 and 2.5 25- ?? internal series oct without calibration v ccio = 3.0, 2.5 40 40 % 25- ? r s 1.8 and 1.5 25- ? internal series oct without calibration v ccio = 1.8, 1.5 40 40 % 25- ? r s 1.2 25- ?? internal series oct without calibration v ccio = 1.2 50 50 % 50- ? r s 3.0 and 2.5 50- ? internal series oct without calibration v ccio = 3.0, 2.5 40 40 % 50- ? r s 1.8 and 1.5 50- ?? internal series oct without calibration v ccio = 1.8, 1.5 40 40 % 50- ? r s 1.2 50- ?? internal series oct without calibration v ccio = 1.2 50 50 % 100- ? r d 2.5 100- ?? internal differential oct v ccio = 2.5 25 25 % equation 1?1. oct variation (note 1) notes to equation 1?1 : (1) r oct value calculated from equation 1?1 shows the range of oct resistance wi th the variation of temperature and v ccio . r oct r scal 1 dr dt ------ - ? t ? ?? dr dv ------- ? v ? ?? ? + ?? ?? = 1?12 chapter 1: device datasheet for arria ii devices electrical characteristics arria ii device handbook volume 3: device datasheet and addendum july 2012 altera corporation use the following with equation 1?1 : r scal is the oct resistance value at power up. ? t is the variation of temperature with respect to the temperature at power up. ? v is the variation of voltage with respect to the v ccio at power up. dr/dt is the percentage change of r scal with temperature. dr/dv is the percentage change of r scal with voltage. table 1?14 lists the oct variation with temp erature and voltage after power-up calibration for arria ii gx devices. table 1?15 lists the oct variation with temp erature and voltage after power-up calibration for arria ii gz devices. pin capacitance table 1?16 lists the pin capacitance for arria ii gx devices. table 1?14. oct variation after power-up calibration for arria ii gx devices nominal voltage v ccio (v) dr/dt (%/c) dr/dv (%/mv) 3.0 0.262 0.035 2.5 0.234 0.039 1.8 0.219 0.086 1.5 0.199 0.136 1.2 0.161 0.288 table 1?15. oct variation after power-up calibration for arria ii gz devices (note 1) nominal voltage, v ccio (v) dr/dt (%/c) dr/dv (%/mv) 3.0 0.189 0.0297 2.5 0.208 0.0344 1.8 0.266 0.0499 1.5 0.273 0.0744 1.2 0.317 0.1241 note to table 1?15 : (1) valid for v ccio range of 5% and temperature range of 0 to 85c. table 1?16. pin capacitance for arria ii gx devices symbol description typical unit c io input capacitance on i/o pins, dual-purpose pins (differential i/o, clock, r up , r dn ), and dedicated clock input pins 7pf chapter 1: device datasheet for arria ii devices 1?13 electrical characteristics july 2012 altera corporation arria ii device han dbook volume 3: device datasheet and addendum table 1?17 lists the pin capacitance for arria ii gz devices. internal weak pull-up and weak pull-down resistors table 1?18 lists the weak pull-up and pull-down resistor values for arria ii gx devices. table 1?17. pin capacitance for arria ii gz devices symbol description typical unit c iotb input capacitance on the top and bottom i/o pins 4 pf c iolr input capacitance on the left and right i/o pins 4 pf c clktb input capacitance on the top and bottom non-dedicated clock input pins 4 pf c clklr input capacitance on the left and right non-dedicated clock input pins 4 pf c outfb input capacitance on the dual-purpose clock output and feedback pins 5 pf c clk1 , c clk3 , c clk8 , and c clk10 input capacitance for dedicated clock input pins 2 pf table 1?18. internal weak pull-up and weak pull-down resistors for arria ii gx devices (note 1) symbol description conditions min typ max unit r pu value of i/o pin pull-up resistor before and during configuration, as well as user mode if the programmable pull-up resistor option is enabled. v ccio = 3.3 v 5% (2) 72541k ? v ccio = 3.0 v 5% (2) 72847k ? v ccio = 2.5 v 5% (2) 83561k ? v ccio = 1.8 v 5% (2) 10 57 108 k ? v ccio = 1.5 v 5% (2) 13 82 163 k ? v ccio = 1.2 v 5% (2) 19 143 351 k ? r pd value of tck pin pull-down resistor v ccio = 3.3 v 5% 6 19 29 k ? v ccio = 3.0 v 5% 6 22 32 k ? v ccio = 2.5 v 5% 6 25 42 k ? v ccio = 1.8 v 5% 7 35 70 k ? v ccio = 1.5 v 5% 8 50 112 k ? notes to table 1?18 : (1) all i/o pins have an option to enable weak pull-up except configuration, test, and jt ag pins. the weak pull-down feature is only available for jtag tck . (2) pin pull-up resistance values may be lower if an external so urce drives the pin higher than v ccio . 1?14 chapter 1: device datasheet for arria ii devices electrical characteristics arria ii device handbook volume 3: device datasheet and addendum july 2012 altera corporation table 1?19 lists the weak pull-up resistor values for arria ii gz devices. hot socketing table 1?20 lists the hot-socketing specification for arria ii gx and gz devices. schmitt trigger input the arria ii gx device supports schmitt trigger input on the tdi , tms , tck , nstatus , nconfig , nce , conf_done , and dclk pins. a schmitt trigger feature introduces hysteresis to the input signal for improved noise immunity, especially for signals with slow edge rates. table 1?21 lists the hysteresis specifications across the supported v ccio range for schmitt trigger inputs in arria ii gx devices. table 1?19. internal weak pull-up resistor for arria ii gz devices (note 1) , (2) symbol description conditions min typ max unit r pu value of the i/o pin pull-up resistor before and during configuration, as well as user mode if the programmable pull-up resistor option is enabled. v ccio = 3.0 v 5% (3) ?25 ?k ? v ccio = 2.5 v 5% (3) ?25 ?k ? v ccio = 1.8 v 5% (3) ?25 ?k ? v ccio = 1.5 v 5% (3) ?25 ?k ? v ccio = 1.2 v 5% (3) ?25 ?k ? notes to table 1?19 : (1) all i/o pins have an option to enable weak pul l-up except configuration, test, and jtag pins. (2) the internal weak pull-down feature is only available for the jtag tck pin. the typical value for this in ternal weak pull-down resistor is approximately 25 k ?? (3) pin pull-up resistance values may be lower if an external so urce drives the pin higher than v ccio . table 1?20. hot socketing specifications for arria ii devices symbol description maximum i iiopin(dc) dc current per i/o pin 300 ? a i iopin(ac) ac current per i/o pin 8 ma (1) i xcvrtx(dc) dc current per transceiver tx pin 100 ma i xcvrrx(dc) dc current per transceiver rx pin 50 ma note to table 1?20 : (1) the i/o ramp rate is 10 ns or more. for ramp rates faster than 10 ns, |i iopin | = c dv/dt, in which ?c? is i/o pin capacitance and ?dv/dt? is slew rate. table 1?21. schmitt trigger input hysteresis specifications for arria ii gx devices symbol description condition (v) minimum unit v schmitt hysteresis for schmitt trigger input v ccio = 3.3 220 mv v ccio = 2.5 180 mv v ccio = 1.8 110 mv v ccio = 1.5 70 mv chapter 1: device datasheet for arria ii devices 1?15 electrical characteristics july 2012 altera corporation arria ii device han dbook volume 3: device datasheet and addendum i/o standard specifications table 1?22 through table 1?35 list input voltage (v ih and v il ), output voltage (v oh and v ol ), and current drive characteristics (i oh and i ol ) for various i/o standards supported by the arria ii device family. they also show the arria ii device family i/o standard specifications. v ol and v oh values are valid at the corresponding i oh and i ol , respectively. 1 for an explanation of terms used in table 1?22 through table 1?35 , refer to ?glossary? on page 1?74 . table 1?22 lists the single-ended i/o standards for arria ii gx devices. table 1?23 lists the single-ended i/o standards for arria ii gz devices. table 1?22. single-ended i/o standards for arria ii gx devices i/o standard v ccio (v) v il (v) v ih (v) v ol (v) v oh (v) i ol (ma) i oh (ma) min typ max min max min max max min 3.3 v lvttl 3.135 3.3 3.465 ?0.3 0.8 1.7 3.6 0.45 2.4 4 ?4 3.3 v lvcmos 3.135 3.3 3.465 ?0.3 0.8 1.7 3.6 0.2 v ccio -0.2 2 ?2 3.0 v lvttl 2.85 3 3.15 ?0.3 0.8 1.7 v ccio + 0.3 0.45 2.4 4 ?4 3.0 v lvcmos 2.85 3 3.15 ?0.3 0.8 1.7 v ccio + 0.3 0.2 v ccio - 0.2 0.1 ?0.1 2.5 v lvcmos 2.375 2.5 2.625 ?0.3 0.7 1.7 v ccio + 0.3 0.4 2 1 ?1 1.8 v lvcmos 1.71 1.8 1.89 ?0.3 0.35 v ccio 0.65 v ccio v ccio + 0.3 0.45 v ccio - 0.45 2?2 1.5 v lvcmos 1.425 1.5 1.575 ?0.3 0.35 v ccio 0.65 v ccio v ccio + 0.3 0.25 v ccio 0.75 v ccio 2?2 1.2 v lvcmos 1.14 1.2 1.26 ?0.3 0.35 v ccio 0.65 v ccio v ccio + 0.3 0.25 v ccio 0.75 v ccio 2?2 3.0-v pci 2.85 3 3.15 ? 0.3 v ccio 0.5 v ccio v ccio + 0.3 0.1 v ccio 0.9 v ccio 1.5 ?0.5 3.0-v pci-x 2.85 3 3.15 ? 0.35 v ccio 0.5 v ccio v ccio + 0.3 0.1 v ccio 0.9 v ccio 1.5 ?0.5 table 1?23. single-ended i/o standards for arria ii gz devices (part 1 of 2) i/o standard v ccio (v) v il (v) v ih (v) v ol (v) v oh (v) i ol (ma) i oh (ma) min typ max min max min max max min lvttl 2.85 3 3.15 -0.3 0.8 1.7 3.6 0.4 2.4 2 -2 lvcmos 2.85 3 3.15 -0.3 0.8 1.7 3.6 0.2 v ccio - 0.2 0.1 -0.1 2.5 v 2.375 2.5 2.625 -0.3 0.7 1.7 3.6 0.4 2 1 -1 1.8 v 1.71 1.8 1.89 -0.3 0.35 v ccio 0.65 v ccio v ccio + 0.3 0.45 v ccio - 0.45 2-2 1.5 v 1.425 1.5 1.575 -0.3 0.35 v ccio 0.65 v ccio v ccio + 0.3 0.25 v ccio 0.75 v ccio 2-2 1?16 chapter 1: device datasheet for arria ii devices electrical characteristics arria ii device handbook volume 3: device datasheet and addendum july 2012 altera corporation table 1?24 lists the single-ended sstl and hstl i/o reference voltage specifications for arria ii gx devices. table 1?25 lists the single-ended sstl and hstl i/o reference voltage specifications for arria ii gz devices. 1.2 v 1.14 1.2 1.26 -0.3 0.35 v ccio 0.65 v ccio v ccio + 0.3 0.25 v ccio 0.75 v ccio 2-2 3.0-v pci 2.85 3 3.15 ? 0.3 v ccio 0.5 v ccio 3.6 0.1 v ccio 0.9 v ccio 1.5 -0.5 3.0-v pci-x 2.85 3 3.15 ? 0.35 v ccio 0.5 v ccio ? 0.1 v ccio 0.9 v ccio 1.5 -0.5 table 1?23. single-ended i/o standards for arria ii gz devices (part 2 of 2) i/o standard v ccio (v) v il (v) v ih (v) v ol (v) v oh (v) i ol (ma) i oh (ma) min typ max min max min max max min table 1?24. single-ended sstl and hstl i/o reference voltage specifications for arria ii gx devices i/o standard v ccio (v) v ref (v) v tt (v) min typ max min typ max min typ max sstl-2 class i, ii 2.375 2.5 2.625 0.49 v ccio 0.5 v ccio 0.51 v ccio v ref - 0.04 v ref v ref + 0.04 sstl-18 class i, ii 1.71 1.8 1.89 0.833 0.9 0.969 v ref - 0.04 v ref v ref + 0.04 sstl-15 class i, ii 1.425 1.5 1.575 0.47 v ccio 0.5 v ccio 0.53 v ccio 0.47 v ccio 0.5 v ccio 0.53 v ccio hstl-18 class i, ii 1.71 1.8 1.89 0.85 0.9 0.95 0.85 0.9 0.95 hstl-15 class i, ii 1.425 1.5 1.575 0.71 0.75 0.79 0.71 0.75 0.79 hstl-12 class i, ii 1.14 1.2 1.26 0.48 v ccio 0.5 v ccio 0.52 v ccio ?v ccio /2 ? table 1?25. single-ended sstl and hstl i/o reference voltage specifications for arria ii gz devices i/o standard v ccio (v) v ref (v) v tt (v) min typ max min typ max min typ max sstl-2 class i, ii 2.375 2.5 2.625 0.49 v ccio 0.5 v ccio 0.51 v ccio v ref - 0.04 v ref v ref + 0.04 sstl-18 class i, ii 1.71 1.8 1.89 0.833 0.9 0.969 v ref - 0.04 v ref v ref + 0.04 sstl-15 class i, ii 1.425 1.5 1.575 0.47 v ccio 0.5 v ccio 0.53 v ccio 0.47 v ccio v ref 0.53 v ccio hstl-18 class i, ii 1.71 1.8 1.89 0.85 0.9 0.95 ? v ccio /2 ? hstl-15 class i, ii 1.425 1.5 1.575 0.68 0.75 0.9 ? v ccio /2 ? hstl-12 class i, ii 1.14 1.2 1.26 0.47 v ccio 0.5 v ccio 0.53 v ccio ?v ccio /2 ? chapter 1: device datasheet for arria ii devices 1?17 electrical characteristics july 2012 altera corporation arria ii device han dbook volume 3: device datasheet and addendum table 1?26 lists the single-ended sstl and hstl i/o standard signal specifications for arria ii gx devices. table 1?27 lists the single-ended sstl and hstl i/o standard signal specifications for arria ii gz devices. table 1?26. single-ended sstl and hstl i/o standard signal specifications for arria ii gx devices i/o standard v il(dc) (v) v ih(dc) (v) v il(ac) (v) v ih(ac) (v) v ol (v) v oh (v) i ol (ma) i oh (ma) min max min max max min max min sstl-2 class i ?0.3 v ref - 0.18 v ref + 0.18 v ccio + 0.3 v ref - 0.35 v ref + 0.35 v tt - 0.57 v tt + 0.57 8.1 ?8.1 sstl-2 class ii ?0.3 v ref - 0.18 v ref + 0.18 v ccio + 0.3 v ref - 0.35 v ref + 0.35 v tt - 0.76 v tt + 0.76 16.4 ?16.4 sstl-18 class i ?0.3 v ref - 0.125 v ref + 0.125 v ccio + 0.3 v ref - 0.25 v ref + 0.25 v tt - 0.475 v tt + 0.475 6.7 ?6.7 sstl-18 class ii ?0.3 v ref - 0.125 v ref + 0.125 v ccio + 0.3 v ref - 0.25 v ref + 0.25 0.28 v ccio - 0.28 13.4 ?13.4 sstl-15 class i ?0.3 v ref - 0.1 v ref + 0.1 v ccio + 0.3 v ref - 0.175 v ref + 0.175 0.2 v ccio 0.8 v ccio 8?8 sstl-15 class ii ?0.3 v ref - 0.1 v ref + 0.1 v ccio + 0.3 v ref - 0.175 v ref + 0.175 0.2 v ccio 0.8 v ccio 16 ?16 hstl-18 class i ?0.3 v ref - 0.1 v ref + 0.1 v ccio + 0.3 v ref - 0.2 v ref + 0.2 0.4 v ccio - 0.4 8?8 hstl-18 class ii ?0.3 v ref - 0.1 v ref + 0.1 v ccio + 0.3 v ref - 0.2 v ref + 0.2 0.4 v ccio - 0.4 16 ?16 hstl-15 class i ?0.3 v ref - 0.1 v ref + 0.1 v ccio + 0.3 v ref - 0.2 v ref + 0.2 0.4 v ccio - 0.4 8?8 hstl-15 class ii ?0.3 v ref - 0.1 v ref + 0.1 v ccio + 0.3 v ref - 0.2 v ref + 0.2 0.4 v ccio - 0.4 16 ?16 hstl-12 class i ?0.15 v ref - 0.08 v ref + 0.08 v ccio + 0.15 v ref - 0.15 v ref + 0.15 0.25 v ccio 0.75 v ccio 8?8 hstl-12 class ii ?0.15 v ref - 0.08 v ref + 0.08 v ccio + 0.15 v ref - 0.15 v ref + 0.15 0.25 v ccio 0.75 v ccio 14 ?14 table 1?27. single-ended sstl and hstl i/o standards signal specifications for arria ii gz devices (part 1 of 2) i/o standard v il(dc) (v) v ih(dc) (v) v il(ac) (v) v ih(ac) (v) v ol (v) v oh (v) i ol (ma) i oh (ma) min max min max max min max min sstl-2 class i -0.3 v ref - 0.15 v ref + 0.15 v ccio + 0.3 v ref - 0.31 v ref + 0.31 v tt - 0.57 v tt + 0.57 8.1 -8.1 sstl-2 class ii -0.3 v ref - 0.15 v ref + 0.15 v ccio + 0.3 v ref - 0.31 v ref + 0.31 v tt - 0.76 v tt + 0.76 16.2 -16.2 sstl-18 class i -0.3 v ref - 0.125 v ref + 0.125 v ccio + 0.3 v ref - 0.25 v ref + 0.25 v tt - 0.475 v tt + 0.475 6.7 -6.7 sstl-18 class ii -0.3 v ref - 0.125 v ref + 0.125 v ccio + 0.3 v ref - 0.25 v ref + 0.25 0.28 v ccio - 0.28 13.4 -13.4 sstl-15 class i ? v ref - 0.1 v ref + 0.1 ? v ref - 0.175 v ref + 0.175 0.2 v ccio 0.8 v ccio 8-8 1?18 chapter 1: device datasheet for arria ii devices electrical characteristics arria ii device handbook volume 3: device datasheet and addendum july 2012 altera corporation table 1?28 lists the differential sstl i/o standards for arria ii gx devices. table 1?29 lists the differential sstl i/o standards for arria ii gz devices sstl-15 class ii ? v ref - 0.1 v ref + 0.1 ? v ref - 0.175 v ref + 0.175 0.2 v ccio 0.8 v ccio 16 -16 hstl-18 class i ? v ref - 0.1 v ref + 0.1 ?v ref - 0.2 v ref + 0.2 0.4 v ccio - 0.4 8-8 hstl-18 class ii ? v ref - 0.1 v ref + 0.1 ?v ref - 0.2 v ref + 0.2 0.4 v ccio - 0.4 16 -16 hstl-15 class i ? v ref - 0.1 v ref + 0.1 ?v ref - 0.2 v ref + 0.2 0.4 v ccio - 0.4 8-8 hstl-15 class ii ? v ref - 0.1 v ref + 0.1 ?v ref - 0.2 v ref + 0.2 0.4 v ccio - 0.4 16 -16 hstl-12 class i -0.15 v ref - 0.08 v ref + 0.08 v ccio + 0.15 v ref - 0.15 v ref + 0.15 0.25 v ccio 0.75 v ccio 8-8 hstl-12 class ii -0.15 v ref - 0.08 v ref + 0.08 v ccio + 0.15 v ref - 0.15 v ref + 0.15 0.25 v ccio 0.75 v ccio 16 -16 table 1?27. single-ended sstl and hstl i/o standards signal specifications for arria ii gz devices (part 2 of 2) i/o standard v il(dc) (v) v ih(dc) (v) v il(ac) (v) v ih(ac) (v) v ol (v) v oh (v) i ol (ma) i oh (ma) min max min max max min max min table 1?28. differential sstl i/o standards for arria ii gx devices i/o standard v ccio (v) v swing(dc) (v) v x(ac) (v) v swing(ac) (v) v ox(ac) (v) min typ max min max min typ max min max min typ max sstl-2 class i, ii 2.375 2.5 2.625 0.36 v ccio v ccio /2 - 0.2 ? v ccio /2 + 0.2 0.7 v ccio v ccio /2 - 0.15 ? v ccio /2 + 0.15 sstl-18 class i, ii 1.71 1.8 1.89 0.25 v ccio v ccio /2 - 0.175 ? v ccio /2 + 0.175 0.5 v ccio v ccio /2 - 0.125 ? v ccio /2 + 0.125 sstl-15 class i, ii 1.425 1.5 1.575 0.2 ? ? v ccio / 2 ?0.35? ? v ccio / 2 ? table 1?29. differential sstl i/o standards for arria ii gz devices i/o standard v ccio (v) v swing(dc) (v) v x(ac) (v) v swing(ac) (v) v ox(ac) (v) min typ max min max min typ max min max min typ max sstl-2 class i, ii 2.375 2.5 2.625 0.3 v ccio + 0.6 v ccio /2 - 0.2 ? v ccio /2 + 0.2 0.62 v ccio + 0.6 v ccio /2 - 0.15 ? v ccio /2 + 0.15 sstl-18 class i, ii 1.71 1.8 1.89 0.25 v ccio + 0.6 v ccio /2 - 0.175 ? v ccio /2 + 0.175 0.5 v ccio + 0.6 v ccio /2 - 0.125 ? v ccio /2 + 0.125 sstl-15 class i, ii 1.425 1.5 1.575 0.2 ? ? v ccio / 2 ?0.35? ? v ccio / 2 ? chapter 1: device datasheet for arria ii devices 1?19 electrical characteristics july 2012 altera corporation arria ii device han dbook volume 3: device datasheet and addendum table 1?30 lists the hstl i/o standards for arria ii gx devices. table 1?31 lists the hstl i/o standards for arria ii gz devices. table 1?32 lists the differential i/o standard specifications for arria ii gx devices. table 1?30. differential hstl i/o standards for arria ii gx devices i/o standard v ccio (v) v dif(dc) (v) v x(ac) (v) v cm(dc) (v) v dif(ac) (v) min typ max min max min typ max min typ max min max hstl-18 class i 1.71 1.8 1.89 0.2 ? 0.85 ? 0.95 0.88 ? 0.95 0.4 ? hstl-15 class i, ii 1.425 1.5 1.575 0.2 ? 0.71 ? 0.79 0.71 ? 0.79 0.4 ? hstl-12 class i, ii 1.14 1.2 1.26 0.16 ? ? 0.5 v ccio ? 0.48 v ccio 0.5 v ccio 0.52 v ccio 0.3 ? table 1?31. differential hstl i/o standards for arria ii gz devices i/o standard v ccio (v) v dif(dc) (v) v x(ac) (v) v cm(dc) (v) v dif(ac) (v) min typ max min max min typ max min typ max min max hstl-18 class i 1.71 1.8 1.89 0.2 ? 0.78 ? 1.12 0.78 ? 1.12 0.4 ? hstl-15 class i, ii 1.425 1.5 1.575 0.2 ? 0.68 ? 0.9 0.68 ? 0.9 0.4 ? hstl-12 class i, ii 1.14 1.2 1.26 0.16 v ccio + 0.3 ? 0.5 v ccio ? 0.4 v ccio 0.5 v ccio 0.6 v ccio 0.3 v ccio + 0.48 table 1?32. differential i/o standard specifications for arria ii gx devices (note 1) i/o standard v ccio (v) v id (mv) v icm (v) (2) v od (v) (3) v ocm (v) min typ max min cond. max min max min typ max min typ max 2.5 v lvds 2.375 2.5 2.625 100 v cm = 1.25 v ? 0.05 1.80 0.247 ? 0.6 1.125 1.25 1.375 rsds (4) 2.375 2.5 2.625 ? ? ? ? ? 0.1 0.2 0.6 0.5 1.2 1.4 mini-lvds (4) 2.375 2.5 2.625 ? ? ? ? ? 0.25 ? 0.6 1 1.2 1.4 lvpecl (5) 2.375 2.5 2.625 300 ? ? 0.6 1.8 ? ? ? ? ? ? blvds (6) 2.375 2.5 2.625 100 ? ? ? ? ? ? ? ? ? ? notes to table 1?32 : (1) the 1.5 v pcml transceiver i/o standa rd specifications are described in ?transceiver performance sp ecifications? on page 1?21 . (2) v in range: 0 <= v in <= 1.85 v. (3) r l range: 90 <= rl <= 110 ? . (4) the rsds and mini-lvds i/o standards ar e only supported for differential outputs. (5) the lvpecl input standard is supported at the dedicated clock in put pins (gclk) only. (6) there are no fixed v icm , v od , and v ocm specifications for blvds. these specifi cations depend on the system topology. 1?20 chapter 1: device datasheet for arria ii devices electrical characteristics arria ii device handbook volume 3: device datasheet and addendum july 2012 altera corporation table 1?33 lists the differential i/o standard specifications for arria ii gz devices. power consumption for the arria ii device family altera offers two ways to estimate power for a design: using the microsoft excel-based early power estimator using the quartus ? ii powerplay power analyzer feature the interactive microsoft excel-based early power estimator is typically used prior to designing the fpga in order to get a magn itude estimate of the device power. the quartus ii powerplay power analyzer provides better quality estimates based on the specifics of the design after place-and-route is complete. the powerplay power analyzer can apply a combination of user-e ntered, simulation-derived, and estimated signal activities which, when combined with detailed circuit models, can yield very accurate power estimates. f for more information about power estimation tools, refer to the powerplay early power estimator user guide and the powerplay power analysis chapter in volume 3 of the quartus ii handbook . table 1?33. differential i/o standard specifications for arria ii gz devices (note 1) i/o standard (2) v ccio (v) v id (mv) v icm(dc) (v) v od (v) (3) v ocm (v) (3) min typ max min cond. max min max min typ max min typ max 2.5 v lvds (hio) 2.375 2.5 2.625 100 v cm = 1.25 v ? 0.05 1.8 0.247 ? 0.6 1.125 1.25 1.375 2.5 v lvds (vio) 2.375 2.5 2.625 100 v cm = 1.25 v ? 0.05 1.8 0.247 ? 0.6 1 1.25 1.5 rsds (hio) 2.375 2.5 2.625 100 v cm = 1.25 v ? 0.3 1.4 0.1 0.2 0.6 0.5 1.2 1.4 rsds (vio) 2.375 2.5 2.625 100 v cm = 1.25 v ? 0.3 1.4 0.1 0.2 0.6 0.5 1.2 1.5 mini-lvds (hio) 2.375 2.5 2.625 200 ? 600 0.4 1.32 5 0.25 ? 0.6 1 1.2 1.4 mini-lvds (vio) 2.375 2.5 2.625 200 ? 600 0.4 1.32 5 0.25 ? 0.6 1 1.2 1.5 lvpecl 2.375 2.5 2.625 300 ? ? 0.6 1.8 ? ? ? ? ? ? blvds (4) 2.375 2.5 2.625 100 ? ? ? ? ? ? ? ? ? ? notes to table 1?33 : (1) 1.4-v/1.5-v pcml transceiver i/o stan dard specifications are described in ?transceiver performance specifications? on page 1?21 . (2) vertical i/o (vio) is top and bottom i/os; horizontal i/o (hio) is left and right i/os. (3) r l range: 90 ? rl ? 110 ? . (4) there are no fixed v icm , v od , and v ocm specifications for blvds. these specifi cations depend on the system topology. chapter 1: device datasheet for arria ii devices 1?21 switching characteristics july 2012 altera corporation arria ii device han dbook volume 3: device datasheet and addendum switching characteristics this section provides performance characteristics of the arri a ii gx and gz core and periphery blocks for commercial grade devices. the following tables are considered final and are based on actual silicon ch aracterization and testing. these numbers reflect the actual performance of the device under worst-case silicon process, voltage, and ju nction temperature conditions. transceiver performa nce specifications table 1?34 lists the arria ii gx transceiver specifications. table 1?34. transceiver specifications for arria ii gx devices (note 1) (part 1 of 7) symbol/ description condition i3 c4 c5 and i5 c6 unit min typ max min typ max min typ max min typ max reference clock supported i/o standards 1.2-v pcml, 1.5-v pcml, 2.5-v pcml, differential lvpecl, lvds, and hcsl input frequency from refclk input pins ? 50 ? 622.08 50 ? 622.08 50 ? 622.08 50 ? 622.08 mhz input frequency from pld input ? 50 ? 200 50 ? 200 50 ? 200 50 ? 200 mhz absolute v max for a refclk pin ? ? ? 2.2 ? ? 2.2 ? ? 2.2 ? ? 2.2 v absolute v min for a refclk pin ? ?0.3 ? ? ?0.3 ? ? ?0.3 ? ? ?0.3 ? ? v rise/fall time (2) ? ? ? 0.2 ? ? 0.2 ? ? 0.2 ? ? 0.2 ui duty cycle ? 45 ? 55 45 ? 55 45 ? 55 45 ? 55 % peak-to-peak differential input voltage ? 200 ? 2000 200 ? 2000 200 ? 2000 200 ? 2000 mv spread-spectrum modulating clock frequency pcie 30 ? 33 30 ? 33 30 ? 33 30 ? 33 khz chapter 1: device datasheet for arria ii devices 1?22 switching characteristics july 2012 altera corporation arria ii device han dbook volume 3: device datasheet and addendum spread-spectrum downspread pcie ? 0 to ?0.5% ?? 0 to ?0.5% ?? 0 to ?0.5% ?? 0 to ?0.5% ?? on-chip termination resistors ? ? 100 ? ? 100 ? ? 100 ? ? 100 ? ? v icm (ac coupled) ? 1100 5% 1100 5% 1100 5% 1100 5% mv v icm (dc coupled) hcsl i/o standard for pcie reference clock 250 ? 550 250 ? 550 250 ? 550 250 ? 550 mv transmitter refclk phase noise 10 hz ? ? -50 ? ? -50 ? ? -50 ? ? -50 dbc/hz 100 hz ? ? -80 ? ? -80 ? ? -80 ? ? -80 dbc/hz 1 khz ? ? -110 ? ? -110 ? ? -110 ? ? -110 dbc/hz 10 khz ? ? -120 ? ? -120 ? ? -120 ? ? -120 dbc/hz 100 khz ? ? -120 ? ? -120 ? ? -120 ? ? -120 dbc/hz ?? 1 mhz ? ? -130 ? ? -130 ? ? -130 ? ? -130 dbc/hz transmitter refclk phase jitter (rms) for 100 mhz refclk (3) 10 khz to 20 mhz ??3??3??3??3ps r ref ?? 2000 1% ?? 2000 1% ?? 2000 1% ?? 2000 1% ? ? transceiver clocks calibration block clock frequency ( cal_blk_clk ) ? 10 ? 125 10 ? 125 10 ? 125 10 ? 125 mhz table 1?34. transceiver specifications for arria ii gx devices (note 1) (part 2 of 7) symbol/ description condition i3 c4 c5 and i5 c6 unit min typ max min typ max min typ max min typ max chapter 1: device datasheet for arria ii devices 1?23 switching characteristics july 2012 altera corporation arria ii device han dbook volume 3: device datasheet and addendum fixedclk clock frequency pcie receiver detect ? 125 ? ? 125 ? ? 125 ? ? 125 ? mhz reconfig_ clk clock frequency dynamic reconfig. clock frequency 2.5/ 37.5 (4) ?50 2.5/ 37.5 (4) ?50 2.5/ 37.5 (4) ?50 2.5/ 37.5 (4) ?50mhz delta time between reconfig_ clks (5) ???2??2??2??2ms transceiver block minimum power-down pulse width ??1??1??1??1?s receiver supported i/o standards 1.4-v pcml, 1.5-v pcml, 2.5-v pcm l, 2.5-v pcml, lvpecl, and lvds data rate ? 600 ? 6375 600 ? 3750 600 ? 3750 600 ? 3125 mbps absolute v max for a receiver pin (6) ? ? ? 1.5 ? ? 1.5 ? ? 1.5 ? ? 1.5 v absolute v min for a receiver pin ? -0.4 ? ? -0.4 ? ? -0.4 ? ? -0.4 ? ? v maximum peak-to-peak differential input voltage v id (diff p-p) v icm = 0.82 v setting ? ? 2.7 ? ? 2.7 ? ? 2.7 ? ? 2.7 v v icm =1.1 v setting (7) ? ? 1.6 ? ? 1.6 ? ? 1.6 ? ? 1.6 v table 1?34. transceiver specifications for arria ii gx devices (note 1) (part 3 of 7) symbol/ description condition i3 c4 c5 and i5 c6 unit min typ max min typ max min typ max min typ max 1?24 chapter 1: device datasheet for arria ii devices switching characteristics arria ii device handbook volume 3: device data sheet and addendum july 2012 altera corporation minimum peak-to-peak differential input voltage v id (diff p-p) ? 100 ? ? 100 ? ? 100 ? ? 100 ? ? mv v icm v icm = 0.82 v setting ? 820 ? ? 820 ? ? 820 ? ? 820 ? mv v icm =1.1 v setting (7) ? 1100 ? ? 1100 ? ? 1100 ? ? 1100 ? mv differential on-chip termination resistors 100 ?? setting ? 100 ? ? 100 ? ? 100 ? ? 100 ? ? return loss differential mode pcie 50 mhz to 1.25 ghz: ?10db xaui 100 mhz to 2.5 ghz: ?10db return loss common mode pcie 50 mhz to 1.25 ghz: ?6db xaui 100 mhz to 2.5 ghz: ?6db programmable ppm detector (8) ? 62.5, 100, 125, 200, 250, 300, 500, 1000 ppm run length ? ? 80 ? ? 80 ? ? 80 ? ? 80 ? ui programmable equalization ???7??7??7??7db signal detect/loss threshold pcie mode 65 ? 175 65 ? 175 65 ? 175 65 ? 175 mv cdr ltr time (9) ? ? ? 75??75??75??75s cdr minimum t1b (10) ? 15 ? ? 15 ? 15 ? ? 15 ? ? s table 1?34. transceiver specifications for arria ii gx devices (note 1) (part 4 of 7) symbol/ description condition i3 c4 c5 and i5 c6 unit min typ max min typ max min typ max min typ max chapter 1: device datasheet for arria ii devices 1?25 switching characteristics july 2012 altera corporation arria ii device han dbook volume 3: device datasheet and addendum ltd lock time (11) ? 0 100 4000 0 100 4000 0 100 4000 0 100 4000 ns data lock time from rx_ freqlocked (12) ? ? ? 4000 ? ? 4000 ? ? 4000 ? ? 4000 ns programmable dc gain dc gain setting = 0 ?0??0??0??0?db dc gain setting = 1 ?3??3??3??3?db dc gain setting = 2 ?6??6??6??6?db transmitter supported i/o standards 1.5-v pcml data rate ? 600 ? 6375 600 ? 3750 600 ? 3750 600 ? 3125 mbps v ocm 0.65 v setting ? 650 ? ? 650 ? ? 650 ? ? 650 ? mv differential on-chip termination resistors 100 ?? setting ? 100 ? ? 100 ? ? 100 ? ? 100 ? ? return loss differential mode pcie 50 mhz to 1.25 ghz: ?10db xaui 312 mhz to 625 mhz: ?10db 625 mhz to 3.125 ghz: ?10db/decade slope return loss common mode pcie 50 mhz to 1.25 ghz: ?6db rise time (2) ? 50 ? 200 50 ? 200 50 ? 200 50 ? 200 ps fall time ? 50 ? 200 50 ? 200 50 ? 200 50 ? 200 ps table 1?34. transceiver specifications for arria ii gx devices (note 1) (part 5 of 7) symbol/ description condition i3 c4 c5 and i5 c6 unit min typ max min typ max min typ max min typ max 1?26 chapter 1: device datasheet for arria ii devices switching characteristics arria ii device handbook volume 3: device data sheet and addendum july 2012 altera corporation intra- differential pair skew ???15??15??15??15ps intra-transceiver block skew pcie 4 ? ? 120 ? ? 120 ? ? 120 ? ? 120 ps inter-transceiver block skew pcie 8 ? ? 300 ? ? 300 ? ? 300 ? ? 300 ps cmu pll0 and cmu pll1 cmu pll lock time from cmupll_ reset deassertion ? ? ? 100 ? ? 100 ? ? 100 ? ? 100 ? s pld-transceiver interface interface speed ? 25 ? 320 25 ? 240 25 ? 240 25 ? 200 mhz table 1?34. transceiver specifications for arria ii gx devices (note 1) (part 6 of 7) symbol/ description condition i3 c4 c5 and i5 c6 unit min typ max min typ max min typ max min typ max chapter 1: device datasheet for arria ii devices 1?27 switching characteristics july 2012 altera corporation arria ii device han dbook volume 3: device datasheet and addendum digital reset pulse width ? minimum is 2 parallel clock cycles notes to table 1?34 : (1) for ac-coupled links, the on-chip biasing circuit is switched off before and during configuration. ensure that input specifi cations are not violated during this period. (2) the rise/fall time is sp ecified from 20% to 80%. (3) to calculate the refclk rms phase jitter re quirement at reference clock frequencies other than 100 mhz, use the following fo rmula: refclk rms phase jitter at f (mhz) = refc lk rms phase jitter at 100 mhz * 100/f. (4) the minimum reconfig_clk frequency is 2.5 mhz if the tran sceiver channel is configured in transmitter only mode. the minimum reconfig_clk frequency is 37.5 mhz if the transceiver channel is configured in receiver only or receiver and transmitter mode. for more information, refer to an 558: implementing dynamic re configuration in arria ii devices . (5) if your design uses more than one dynami c reconfiguration controller instances ( altgx_reconfig ) to control the transceiver channels ( altgx ) physically located on the same side of the device, and if you use different reconfig_clk sources for these altgx_reconfig instances, the delta time between any two of these reconfig_clk sources becoming stable must not exceed the maximum specification listed. (6) the device cannot tolerate prolonged operation at this absolute maximum. (7) you must use the 1.1-v rx v icm setting if the input serial data standard is lvds an d the link is dc-coupled. (8) the rate matcher supports only up to 300 parts per million (ppm). (9) time taken to rx_pll_locked goes high from rx_analogreset de-assertion. refer to figure 1?1 . (10) the time in which the cdr must be kept in lock-to-reference mode after rx_pll_locked goes high and before rx_locktodata is asserted in manual mode. refer to figure 1?1 . (11) the time taken to reco ver valid data after the rx_locktodata signal is asserted in manual mode. refer to figure 1?1 . (12) the time taken to reco ver valid data after the rx_freqlocked signal goes high in au tomatic mode. refer to figure 1?2 . table 1?34. transceiver specifications for arria ii gx devices (note 1) (part 7 of 7) symbol/ description condition i3 c4 c5 and i5 c6 unit min typ max min typ max min typ max min typ max 1?28 chapter 1: device datasheet for arria ii devices switching characteristics arria ii device handbook volume 3: device datasheet and addendum july 2012 altera corporation table 1?35 lists the transceiver specific ations for arria ii gz devices. table 1?35. transceiver specifications for arria ii gz devices (part 1 of 5) symbol/ description conditions ?c3 and ?i3 (1) ?c4 and ?i4 unit min typ max min typ max reference clock supported i/o standards 1.2-v pcml, 1.5-v pcml, 2.5-v pcml, differential lvpecl, lvds, and hcsl input frequency from refclk input pins ? 50 ? 697 50 ? 637.5 mhz phase frequency detector (cmu pll and receiver cdr) ? 50 ? 325 50 ? 325 mhz absolute v max for a refclk pin ???1.6??1.6v operational v max for a refclk pin ???1.5??1.5v absolute v min for a refclk pin ? -0.4 ? ? -0.4 ? ? v rise/fall time (2) ? ? ? 0.2 ? ? 0.2 ui duty cycle ? 45 ? 55 45 ? 55 % peak-to-peak differential input voltage ? 200 ? 1600 200 ? 1600 mv spread-spectrum modulating clock frequency pcie 30 ? 33 30 ? 33 khz spread-spectrum downspread pcie ? 0 to -0.5% ?? 0 to -0.5% ?? on-chip termination resistors ? ? 100 ? ? 100 ? ? v icm (ac coupled) ? 1100 10% 1100 10% mv v icm (dc coupled) hcsl i/o standard for pcie reference clock 250 ? 550 250 ? 550 mv transmitter refclk phase noise 10 hz ? ? -50 ? ? -50 dbc/hz 100 hz ? ? -80 ? ? -80 dbc/hz 1 khz ? ? -110 ? ? -110 dbc/hz 10 khz ? ? -120 ? ? -120 dbc/hz 100 khz ? ? -120 ? ? -120 dbc/hz ? 1 mhz ? ? -130 ? ? -130 dbc/hz transmitter refclk phase jitter (rms) for 100 mhz refclk (3) 10 khz to 20 mhz ? ? 3 ? ? 3 ps r ref ?? 2000 1% ?? 2000 1% ? ? chapter 1: device datasheet for arria ii devices 1?29 switching characteristics july 2012 altera corporation arria ii device han dbook volume 3: device datasheet and addendum transceiver clocks calibration block clock frequency ( cal_blk_clk ) ? 10 ? 125 10 ? 125 mhz fixedclk clock frequency pcie receiver detect ? 125 ? ? 125 ? mhz reconfig_clk clock frequency dynamic reconfiguration clock frequency 2.5/ 37.5 (4) ?50 2.5/ 37.5 (4) ?50mhz delta time between reconfig_clks (5) ???2??2ms transceiver block minimum power-down ( gxb_powerdown ) pulse width ?1??1??s receiver supported i/o standards 1.4-v pcml, 1.5-v pcml, 2.5-v pcml, lvpecl, and lvds data rate ? 600 ? 6375 600 ? 3750 mbps absolute v max for a receiver pin (6) ???1.6??1.6v operational v max for a receiver pin ???1.5??1.5v absolute v min for a receiver pin ? -0.4 ? ? -0.4 ? ? v maximum peak-to-peak differential input voltage v id (diff p-p) before device configuration ???1.6??1.6v maximum peak-to-peak differential input voltage v id (diff p-p) after device configuration v icm = 0.82 v setting ? ? 2.7 ? ? 2.7 v v icm =1.1 v setting (7) ? ? 1.6 ? ? 1.6 v minimum differential eye opening at receiver serial input pins (8) data rate = 600 mbps to 5 gbps equalization = 0 dc gain = 0 db 100 ? ? 165 ? ? mv data rate > 5 gbps equalization = 0 dc gain = 0 db 165 ? ? 165 ? ? mv v icm v icm = 0.82 v setting 820 10% 820 10% mv v icm = 1.1 v setting (7) 1100 10% 1100 10% mv table 1?35. transceiver specifications for arria ii gz devices (part 2 of 5) symbol/ description conditions ?c3 and ?i3 (1) ?c4 and ?i4 unit min typ max min typ max 1?30 chapter 1: device datasheet for arria ii devices switching characteristics arria ii device handbook volume 3: device datasheet and addendum july 2012 altera corporation receiver dc coupling support ? for more information about receiver dc coupling support, refer to the ?dc-coupled links? section in the transceiver architecture for arria ii devices chapter. differential on-chip termination resistors 85 ?? setting 85 20% 85 20% ? 100 ?? setting 100 20% 100 20% ? 120 ?? setting 120 20% 120 20% ? 150- ? setting 150 20% 150 20% ? differential and common mode return loss pcie (gen 1 and gen 2), xaui, higig+, cei sr/lr, srio sr/lr, cpri lv/hv, obsai, sata compliant ? programmable ppm detector (9) ? 62.5, 100, 125, 200, 250, 300, 500, 1,000 ppm run length ? ? ? 200 ? ? 200 ui programmable equalization ? ? ? 16 ? ? 16 db t ltr (10) ???75??75s t ltr_ltd_manual (11) ?15??15??s t ltd_manual (12) ? ? ? 4000 ? ? 4000 ns t ltd_auto (13) ? ? ? 4000 ? ? 4000 ns receiver cdr 3 db bandwidth in lock-to-data (ltd) mode pcie gen1 2.0 - 3.5 mhz pcie gen2 40 - 65 mhz (oif) cei phy at 6.375 gbps 20 - 35 mhz xaui 10 - 18 mhz srio 1.25 gbps 10 - 18 mhz srio 2.5 gbps 10 - 18 mhz srio 3.125 gbps 6 - 10 mhz gige 6 - 10 mhz sonet oc12 3 - 6 mhz sonet oc48 14 - 19 mhz receiver buffer and cdr offset cancellation time (per channel) ? ? ? 17000 ? ? 17000 recon fig_ clk cycles programmable dc gain dc gain setting = 0 ? 0 ? ? 0 ? db dc gain setting = 1 ? 3 ? ? 3 ? db dc gain setting = 2 ? 6 ? ? 6 ? db table 1?35. transceiver specifications for arria ii gz devices (part 3 of 5) symbol/ description conditions ?c3 and ?i3 (1) ?c4 and ?i4 unit min typ max min typ max chapter 1: device datasheet for arria ii devices 1?31 switching characteristics july 2012 altera corporation arria ii device han dbook volume 3: device datasheet and addendum transmitter supported i/o standards 1.5-v pcml data rate (14) ? 600 ? 6375 600 ? 3750 mbps v ocm 0.65 v setting ? 650 ? ? 650 ? mv differential on-chip termination resistors 85 ?? setting 85 15% 85 15% ? 100 ?? setting 100 15% 100 15% ? 120 ?? setting 120 15% 120 15% ? 150- ? setting 150 15% 150 15% ? differential and common mode return loss pcie gen1 and gen2 (tx v od =4), xaui (tx v od =6), higig+ (tx v od =6), cei sr/lr (tx v od =8), srio sr (v od =6), srio lr (v od =8), cpri lv (v od =6), cpri hv (v od =2), obsai (v od =6), sata (v od =4), compliant ? rise time (15) ? 50 ? 200 50 ? 200 ps fall time (15) ? 50 ? 200 50 ? 200 ps intra-differential pair skew ? ? ? 15 ? ? 15 ps intra-transceiver block transmitter channel-to-channel skew 4 pma and pcs bonded mode example: xaui, pcie 4, basic 4 ?? 120??120ps inter-transceiver block transmitter channel-to-channel skew 8 pma and pcs bonded mode example: pcie 8, basic 8 ?? 500??500ps cmu0 pll and cmu1 pll supported data range ? 600 ? 6375 600 ? 3750 mbps pll_powerdown minimum pulse width ( tpll_powerdown ) ?1 1 ? s cmu pll lock time from pll_powerdown de-assertion ? ? ? 100 ? ? 100 ? s table 1?35. transceiver specifications for arria ii gz devices (part 4 of 5) symbol/ description conditions ?c3 and ?i3 (1) ?c4 and ?i4 unit min typ max min typ max 1?32 chapter 1: device datasheet for arria ii devices switching characteristics arria ii device handbook volume 3: device datasheet and addendum july 2012 altera corporation -3 db bandwidth pcie gen1 2.5 - 3.5 mhz pcie gen2 6 - 8 mhz (oif) cei phy at 4.976 gbps 7 - 11 mhz (oif) cei phy at 6.375 gbps 5 - 10 mhz xaui 2 - 4 mhz srio 1.25 gbps 3 - 5.5 mhz srio 2.5 gbps 3 - 5.5 mhz srio 3.125 gbps 2 - 4 mhz gige 2.5 - 4.5 mhz sonet oc12 1.5 - 2.5 mhz sonet oc48 3.5 - 6 mhz transceiver-fpga fabric interface interface speed ? 25 ? 325 25 ? 250 mhz digital reset pulse width ? minimum is two parallel clock cycles ? notes to table 1?35 : (1) the 3x speed grade is the fastest speed grade offered in the following arria ii gz devices: ep2agz225, ep2agz300, and ep2agz 350. (2) the rise and fall time transiti on is specified from 20% to 80%. (3) to calculate the refclk rms phase jitter requirement at reference clock frequencies other than 100 mhz, use the following fo rmula: refclk rms phase jitter at f (mhz) = re fclk rms phase jitter at 100 mhz * 100/f. (4) the minimum reconfig_clk frequency is 2.5 mhz if the tran sceiver channel is configured in transmitter only mode. the minimum reconfig_clk frequency is 37.5 mhz if the tran sceiver channel is configured in receiver only or receiver and transmitter mode. (5) if your design uses more than one dynamic reconfiguration controller ( altgx_reconfig ) instances to control the transceiver ( altgx ) channels physical ly located on the same side of th e device and if you use different reconfig_clk sources for these altgx_reconfig instances, the delta time between any two of these reconfig_clk sources becoming stable must not exce ed the maximum specification listed. (6) the device cannot tolerate prolonged operation at this absolute maximum. (7) you must use the 1.1-v rx v icm setting if the input serial data standard is lvds. (8) the differential eye opening specification at the receiver input pins assumes that receiver equali zation is disabled. if you enable receiver equalization, the receiver circuitry can to lerate a lower minimum eye opening, depend ing on the equalization level. use h-spice simulation to derive the minimum eye opening requirement with receiv er equalizati on enabled. (9) the rate matcher supports only up to 300 ppm. (10) time taken to rx_pll_locked goes high from rx_analogreset de-assertion. refer to figure 1?1 on page 1?33 . (11) time for which the cdr must be kept in lock-to-reference mode after rx_pll_locked goes high and before rx_locktodata is asserted in manual mode. refer to figure 1?1 on page 1?33 . (12) time taken to recover valid data after the rx_locktodata signal is asserted in manual mode. refer to figure 1?1 on page 1?33 . (13) time taken to recover valid data after the rx_freqlocked signal goes high in automatic mode. refer to figure 1?2 on page 1?33 . (14) a gpll may be required to m eet the pma-fpga fabric interface timing above ce rtain data rates. for more information, refer t o the transceiver clocking for arria ii devices chapter. (15) the quartus ii software automa tically selects the approp riate slew rate depending on the configured data rate or functional mode. table 1?35. transceiver specifications for arria ii gz devices (part 5 of 5) symbol/ description conditions ?c3 and ?i3 (1) ?c4 and ?i4 unit min typ max min typ max chapter 1: device datasheet for arria ii devices 1?33 switching characteristics july 2012 altera corporation arria ii device han dbook volume 3: device datasheet and addendum figure 1?1 shows the lock time parameters in manual mode. 1 ltd = lock-to-data. ltr = lock-to-reference. figure 1?2 shows the lock time para meters in automatic mode. figure 1?1. lock time parameters for manual mode ltr ltd invalid data valid data r x_locktodata ltd lock time cdr status r x_dataout r x_pll_locked r x_analogreset cdr ltr time cdr minimum t1b figure 1?2. lock time parameters for automatic mode ltr ltd invalid data valid data r x_freqlocked data lock time from rx_freqlocked r x_dataout cdr status 1?34 chapter 1: device datasheet for arria ii devices switching characteristics arria ii device handbook volume 3: device datasheet and addendum july 2012 altera corporation figure 1?3 shows the differential receiver input waveform. figure 1?4 shows the transmitter output waveform. table 1?36 lists the typical v od for tx term that equals 85 ? .for arria ii gz devices. figure 1?3. receiver input waveform single-ended waveform differential waveform v id (diff peak-peak) = 2 x v id (single-ended) positive channel (p) negative channel (n) ground v id v id v id p ? n = 0 v v cm figure 1?4. transmitter output waveform single-ended waveform differential waveform v od (diff peak-peak) = 2 x v od (single-ended) positive channel (p) negative channel (n) ground v od v od v od p ? n = 0 v v cm table 1?36. typical v od setting, tx term = 85 ?? for arria ii gz devices symbol v od setting (mv) 01234567 v od differential peak-to-peak typical (mv) 170 20% 340 20% 510 20% 595 20% 680 20% 765 20% 850 20% 1020 20% chapter 1: device datasheet for arria ii devices 1?35 switching characteristics july 2012 altera corporation arria ii device han dbook volume 3: device datasheet and addendum table 1?37 lists the typical v od for tx term that equals 100 ? . for arria ii gx and gz devices. table 1?38 lists the typical transmitter pre-emphasis levels in db for the first post tap under the following conditions: low-frequency data pattern (five 1s and five 0s) at 6.375 gbps. the levels listed in table 1?38 are a representation of possible pre-emphasis levels under these specified conditions only, the pre-emphasis levels may change with data pattern and data rate. to predict the pre-emphasis level for your specific data rate and pattern, run simulations using the arria ii gx hssi hspice models. table 1?37. typical v od setting, tx termination = 100 ? for arria ii devices quartus ii setting v od setting (mv) 1 400 2 600 3 (arria ii gz) 700 4 800 5 900 6 1000 7 1200 table 1?38. transmitter pre-emphasis levels for arria ii gx devices arria ii gx (quartus ii software) first post tap setting arria ii gx (quartus ii software) vod setting 124567unit 0 (off)000000? 10.700000db 2 2.7 1.2 0.3 0 0 0 db 3 4.9 2.4 1.2 0.8 0.5 0.2 db 4 7.5 3.8 2.1 1.6 1.2 0.6 db 5 ? 5.3 3.1 2.4 1.8 1.1 db 6 ? 7 4.3 3.3 2.7 1.7 db 1?36 chapter 1: device datasheet for arria ii devices switching characteristics arria ii device handbook volume 3: device datasheet and addendum july 2012 altera corporation table 1?39 lists typical transmitter pre-emphasis levels for arria ii gz devices (in db) for the first post tap under the following co nditions (low-frequency data pattern [five 1s and five 0s] at 6.25 gbps ). the levels listed in table 1?39 are a representation of possible pre-emphasis levels under the sp ecified conditions only and that the pre- emphasis levels may change with data pattern and data rate. f to predict the pre-emphasis level for your specific data rate and pattern, run simulations using the arria ii hssi hspice models. table 1?39. transmitter pre-emphasis levels for arria ii gz devices (part 1 of 2) pre- emphasis 1st post-tap setting v od setting 01234567 0 00000000 1n/a0.7000000 2n/a10.300000 3n/a1.50.600000 4n/a20.70.30 0 0 0 5 n/a 2.7 1.2 0.5 0.3 0 0 0 6 n/a 3.1 1.3 0.8 0.5 0.2 0 0 7 n/a 3.7 1.8 1.1 0.7 0.4 0.2 0 8 n/a 4.2 2.1 1.3 0.9 0.6 0.3 0 9 n/a 4.9 2.4 1.6 1.2 0.8 0.5 0.2 10 n/a 5.4 2.8 1.9 1.4 1 0.7 0.3 11 n/a 6 3.2 2.2 1.7 1.2 0.9 0.4 12 n/a 6.8 3.5 2.6 1.9 1.4 1.1 0.6 13 n/a 7.5 3.8 2.8 2.1 1.6 1.2 0.6 14 n/a 8.1 4.2 3.1 2.3 1.7 1.3 0.7 15 n/a 8.8 4.5 3.4 2.6 1.9 1.5 0.8 16 n/a n/a 4.9 3.7 2.9 2.2 1.7 0.9 17 n/a n/a 5.3 4 3.1 2.4 1.8 1.1 18 n/a n/a 5.7 4.4 3.4 2.6 2 1.2 19 n/a n/a 6.1 4.7 3.6 2.8 2.2 1.4 20 n/a n/a 6.6 5.1 4 3.1 2.4 1.5 21 n/a n/a 7 5.4 4.3 3.3 2.7 1.7 22 n/a n/a 8 6.1 4.8 3.8 3 2 23 n/a n/a 9 6.8 5.4 4.3 3.4 2.3 24 n/a n/a 10 7.6 6 4.8 3.9 2.6 25 n/a n/a 11.4 8.4 6.8 5.4 4.4 3 26 n/a n/a 12.6 9.4 7.4 5.9 4.9 3.3 27 n/a n/a n/a 10.3 8.1 6.4 5.3 3.6 28 n/a n/a n/a 11.3 8.8 7.1 5.8 4 chapter 1: device datasheet for arria ii devices 1?37 switching characteristics july 2012 altera corporation arria ii device han dbook volume 3: device datasheet and addendum table 1?40 lists the transceiver ji tter specifications for all supported protocols for arria ii gx devices. 29 n/a n/a n/a 12.5 9.6 7.7 6.3 4.3 30 n/a n/a n/a n/a 11.4 9 7.4 n/a 31 n/a n/a n/a n/a 12.9 10 8.2 n/a table 1?39. transmitter pre-emphasis levels for arria ii gz devices (part 2 of 2) pre- emphasis 1st post-tap setting v od setting 01234567 table 1?40. transceiver block jitter specifications for arria ii gx devices (note 1) (part 1 of 10) symbol/ description conditions i3 c4 c5, i5 c6 unit min typ max min typ max min typ max min typ max sonet/sdh transmit jitter generation (2) peak-to-peak jitter at 622.08 mbps pattern = prbs15 ? ? 0.1 ? ? 0.1 ? ? 0.1 ? ? 0.1 ui rms jitter at 622.08 mbps pattern = prbs15 ? ? 0.01 ? ? 0.01 ? ? 0.01 ? ? 0.01 ui peak-to-peak jitter at 2488.32 mbps pattern = prbs15 ? ? 0.1 ? ? 0.1 ? ? 0.1 ? ? 0.1 ui rms jitter at 2488.32 mbps pattern = prbs15 ? ? 0.01 ? ? 0.01 ? ? 0.01 ? ? 0.01 ui sonet/sdh receiver jitter tolerance (2) jitter tolerance at 622.08 mbps jitter frequency = 0.03 khz pattern = prbs15 > 15 > 15 > 15 > 15 ui jitter frequency = 25 khz pattern = prbs15 > 1.5 > 1.5 > 1.5 > 1.5 ui jitter frequency = 250 khz pattern = prbs15 > 0.15 > 0.15 > 0.15 > 0.15 ui 1?38 chapter 1: device datasheet for arria ii devices switching characteristics arria ii device handbook volume 3: device datasheet and addendum july 2012 altera corporation jitter tolerance at 2488.32 mbps jitter frequency = 0.06 khz pattern = prbs15 > 15 > 15 > 15 > 15 ui jitter frequency = 100 khz pattern = prbs15 > 1.5 > 1.5 > 1.5 > 1.5 ui jitter frequency = 1mhz pattern = prbs15 > 0.15 > 0.15 > 0.15 > 0.15 ui jitter frequency = 10 mhz pattern = prbs15 > 0.15 > 0.15 > 0.15 > 0.15 ui xaui transmit jitter generation (3) total jitter at 3.125 gbps pattern = cjpat ? ? 0.3 ? ? 0.3 ? ? 0.3 ? ? 0.3 ui deterministic jitter at 3.125 gbps pattern = cjpat ? ? 0.17 ? ? 0.17 ? ? 0.17 ? ? 0.17 ui xaui receiver jitter tolerance (3) total jitter ? > 0.65 > 0.65 > 0.65 > 0.65 ui deterministic jitter ? > 0.37 > 0.37 > 0.37 > 0.37 ui peak-to-peak jitter jitter frequency = 22.1 khz > 8.5 > 8.5 > 8.5 > 8.5 ui peak-to-peak jitter jitter frequency = 1.875 mhz > 0.1 > 0.1 > 0.1 > 0.1 ui peak-to-peak jitter jitter frequency = 20 mhz > 0.1 > 0.1 > 0.1 > 0.1 ui pcie transmit jitter generation (4) total jitter at 2.5 gbps (gen1) compliance pattern ? ? 0.25 ? ? 0.25 ? ? 0.25 ? ? 0.25 ui table 1?40. transceiver block jitter specifications for arria ii gx devices (note 1) (part 2 of 10) symbol/ description conditions i3 c4 c5, i5 c6 unit min typ max min typ max min typ max min typ max chapter 1: device datasheet for arria ii devices 1?39 switching characteristics july 2012 altera corporation arria ii device han dbook volume 3: device datasheet and addendum pcie receiver jitter tolerance (4) total jitter at 2.5 gbps (gen1) compliance pattern > 0.6 > 0.6 > 0.6 > 0.6 ui pcie (gen 1) electrical idle detect threshold (9) vrx-idle- detdiff (p-p) compliance pattern 65 ? 175 65 ? 175 65 ? 175 65 ? 175 mv serial rapidio ? (srio) transmit jitter generation (5) deterministic jitter (peak-to-peak) data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat ? ? 0.17 ? ? 0.17 ? ? 0.17 ? ? 0.17 ui total jitter (peak-to-peak) data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat ? ? 0.35 ? ? 0.35 ? ? 0.35 ? ? 0.35 ui srio receiver jitter tolerance (5) deterministic jitter tolerance (peak-to-peak) data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat > 0.37 > 0.37 > 0.37 > 0.37 ui combined deterministic and random jitter tolerance (peak-to-peak) data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat > 0.55 > 0.55 > 0.55 > 0.55 ui sinusoidal jitter tolerance (peak-to-peak) jitter frequency = 22.1 khz data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat > 8.5 > 8.5 > 8.5 > 8.5 ui jitter frequency = 1.875 mhz data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat > 0.1 > 0.1 > 0.1 > 0.1 ui jitter frequency = 20 mhz data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat > 0.1 > 0.1 > 0.1 > 0.1 ui gige transmit jitter generation (6) deterministic jitter (peak-to-peak) pattern = crpat ? ? 0.14 ? ? 0.14 ? ? 0.14 ? ? 0.14 ui table 1?40. transceiver block jitter specifications for arria ii gx devices (note 1) (part 3 of 10) symbol/ description conditions i3 c4 c5, i5 c6 unit min typ max min typ max min typ max min typ max 1?40 chapter 1: device datasheet for arria ii devices switching characteristics arria ii device handbook volume 3: device datasheet and addendum july 2012 altera corporation total jitter (peak-to-peak) pattern = crpat ? ? 0.27 9 ? ? 0.279 ? ? 0.279 ? ? 0.279 ui gige receiver jitter tolerance (6) deterministic jitter tolerance (peak-to-peak) pattern = cjpat > 0.4 > 0.4 > 0.4 > 0.4 ui combined deterministic and random jitter tolerance (peak-to-peak) pattern = cjpat > 0.66 > 0.66 > 0.66 > 0.66 ui higig transmit jitter generation (7) deterministic jitter (peak-to-peak) data rate = 3.75 gbps pattern = cjpat ? ? 0.17 ? ? 0.17 ? ? ? ? ? ? ui total jitter (peak-to-peak) data rate = 3.75 gbps pattern = cjpat ? ? 0.35 ? ? 0.35 ? ? ? ? ? ? ui higig receiver jitter tolerance (7) deterministic jitter tolerance (peak-to-peak) data rate = 3.75 gbps pattern = cjpat > 0.37 > 0.37 ? ? ? ? ? ? ui combined deterministic and random jitter tolerance (peak-to-peak) data rate = 3.75 gbps pattern = cjpat > 0.65 > 0.65 ? ? ? ? ? ? ui sinusoidal jitter tolerance (peak-to-peak) jitter frequency = 22.1 khz data rate = 3.75 gbps pattern = cjpat > 8.5 > 8.5 ? ? ? ? ? ? ui jitter frequency = 1.875mhz data rate = 3.75 gbps pattern = cjpat > 0.1 > 0.1 ? ? ? ? ? ? ui jitter frequency = 20 mhz data rate = 3.75 gbps pattern = cjpat > 0.1 > 0.1 ? ? ? ? ? ? ui table 1?40. transceiver block jitter specifications for arria ii gx devices (note 1) (part 4 of 10) symbol/ description conditions i3 c4 c5, i5 c6 unit min typ max min typ max min typ max min typ max chapter 1: device datasheet for arria ii devices 1?41 switching characteristics july 2012 altera corporation arria ii device han dbook volume 3: device datasheet and addendum sdi transmitter jitter generation (8) alignment jitter (peak-to-peak) data rate = 1.485 gbps (hd) pattern = color bar low- frequency roll-off = 100 khz 0.2 ? ? 0.2 ? ? 0.2 ? ? 0.2 ? ? ui data rate = 2.97 gbps (3g) pattern = color bar low- frequency roll-off = 100 khz 0.3 ? ? 0.3 ? ? 0.3 ? ? 0.3 ? ? ui sdi receiver jitter tolerance (8) sinusoidal jitter tolerance (peak-to-peak) jitter frequency = 15 khz data rate = 2.97 gbps (3g) pattern = single line scramble color bar > 2 > 2 > 2 > 2 ui jitter frequency = 100 khz data rate = 2.97 gbps (3g) pattern = single line scramble color bar > 0.3 > 0.3 > 0.3 > 0.3 ui jitter frequency = 148.5 mhz data rate = 2.97 gbps (3g) pattern = single line scramble color bar > 0.3 > 0.3 > 0.3 > 0.3 ui table 1?40. transceiver block jitter specifications for arria ii gx devices (note 1) (part 5 of 10) symbol/ description conditions i3 c4 c5, i5 c6 unit min typ max min typ max min typ max min typ max 1?42 chapter 1: device datasheet for arria ii devices switching characteristics arria ii device handbook volume 3: device datasheet and addendum july 2012 altera corporation sinusoidal jitter tolerance (peak-to-peak) jitter frequency = 20 khz data rate = 1.485 gbps (hd) pattern = 75% color bar > 1 > 1 > 1 > 1 ui jitter frequency = 100 khz data rate = 1.485 gbps (hd) pattern = 75% color bar > 0.2 > 0.2 > 0.2 > 0.2 ui jitter frequency = 148.5 mhz data rate = 1.485 gbps (hd) pattern =75% color bar > 0.2 > 0.2 > 0.2 > 0.2 ui sata transmit jitter generation (10) total jitter at 1.5 gbps (g1) compliance pattern ? ? 0.55 ? ? 0.55 ? ? 0.55 ? ? 0.55 ui deterministic jitter at 1.5 gbps (g1) compliance pattern ? ? 0.35 ? ? 0.35 ? ? 0.35 ? ? 0.35 ui total jitter at 3.0 gbps (g2) compliance pattern ? ? 0.55 ? ? 0.55 ? ? 0.55 ? ? 0.55 ui deterministic jitter at 3.0 gbps (g2) compliance pattern ? ? 0.35 ? ? 0.35 ? ? 0.35 ? ? 0.35 ui total jitter at 6.0 gbps (g3) compliance pattern ? ? 0.52 ? ? ? ? ? ? ? ? ? ui random jitter at 6.0 gbps (g3) compliance pattern ? ? 0.18 ? ? ? ? ? ? ? ? ? ui sata receiver jitter tolerance (10) total jitter tolerance at 1.5 gbps (g1) compliance pattern > 0.65 > 0.65 > 0.65 > 0.65 ui deterministic jitter tolerance at 1.5 gbps (g1) compliance pattern > 0.35 > 0.35 > 0.35 > 0.35 ui ssc modulation frequency at 1.5 gbps (g1) compliance pattern 33 33 33 33 khz table 1?40. transceiver block jitter specifications for arria ii gx devices (note 1) (part 6 of 10) symbol/ description conditions i3 c4 c5, i5 c6 unit min typ max min typ max min typ max min typ max chapter 1: device datasheet for arria ii devices 1?43 switching characteristics july 2012 altera corporation arria ii device han dbook volume 3: device datasheet and addendum ssc modulation deviation at 1.5 gbps (g1) compliance pattern 5700 5700 5700 5700 ppm rx differential skew at 1.5 gbps (g1) compliance pattern 80 80 80 80 ps rx ac common mode voltage at 1.5 gbps (g1) compliance pattern 150 150 150 150 mv total jitter tolerance at 3.0 gbps (g2) compliance pattern > 0.65 > 0.65 > 0.65 > 0.65 ui deterministic jitter tolerance at 3.0 gbps (g2) compliance pattern > 0.35 > 0.35 > 0.35 > 0.35 ui ssc modulation frequency at 3.0 gbps (g2) compliance pattern 33 33 33 33 khz ssc modulation deviation at 3.0 gbps (g2) compliance pattern 5700 5700 5700 5700 ppm rx differential skew at 3.0 gbps (g2) compliance pattern 75 75 75 75 ps rx ac common mode voltage at 3.0 gbps (g2) compliance pattern 150 150 150 150 mv total jitter tolerance at 6.0 gbps (g3) compliance pattern > 0.60 > 0.60 > 0.60 > 0.60 ui random jitter tolerance at 6.0 gbps (g3) compliance pattern > 0.18 > 0.18 > 0.18 > 0.18 ui ssc modulation frequency at 6.0 gbps (g3) compliance pattern 33 33 33 33 khz ssc modulation deviation at 6.0 gbps (g3) compliance pattern 5700 5700 5700 5700 ppm rx differential skew at 6.0 gbps (g3) compliance pattern 30 30 30 30 ps rx ac common mode voltage at 6.0 gbps (g3) compliance pattern 100 100 100 100 mv table 1?40. transceiver block jitter specifications for arria ii gx devices (note 1) (part 7 of 10) symbol/ description conditions i3 c4 c5, i5 c6 unit min typ max min typ max min typ max min typ max 1?44 chapter 1: device datasheet for arria ii devices switching characteristics arria ii device handbook volume 3: device datasheet and addendum july 2012 altera corporation cpri transmit jitter generation (11) total jitter e.6.hv, e.12.hv pattern = cjpat ?? 0.27 9 ? ? 0.279 ? ? 0.279 ? ? 0.279 ui e.6.lv, e.12.lv, e.24.lv, e.30.lv pattern = cjtpat ? ? 0.35 ? ? 0.35 ? ? 0.35 ? ? 0.35 ui deterministic jitter e.6.hv, e.12.hv pattern = cjpat ? ? 0.14 ? ? 0.14 ? ? 0.14 ? ? 0.14 ui e.6.lv, e.12.lv, e.24.lv, e.30.lv pattern = cjtpat ? ? 0.17 ? ? 0.17 ? ? 0.17 ? ? 0.17 ui cpri receiver jitter tolerance (11) total jitter tolerance e.6.hv, e.12.hv pattern = cjpat > 0.66 > 0.66 > 0.66 > 0.66 ui deterministic jitter tolerance e.6.hv, e.12.hv pattern = cjpat > 0.4 > 0.4 > 0.4 > 0.4 ui total jitter tolerance e.6.lv, e.12.lv, e.24.lv, e.30.lv pattern = cjtpat > 0.65 > 0.65 > 0.65 > 0.65 ui e.60.lv pattern = prbs31 > 0.6 ? ? ? ui deterministic jitter tolerance e.6.lv, e.12.lv, e.24.lv, e.30.lv pattern = cjtpat > 0.37 > 0.37 > 0.37 > 0.37 ui e.60.lv pattern = prbs31 > 0.45 ? ? ? ui combined deterministic and random jitter tolerance e.6.lv, e.12.lv, e.24.lv, e.30.lv pattern = cjtpat > 0.55 > 0.55 > 0.55 > 0.55 ui obsai transmit jitter generation (12) total jitter at 768 mbps, 1536 mbps, and 3072 mbps refclk = 153.6 mhz pattern = cjpat ? ? 0.35 ? ? 0.35 ? ? 0.35 ? ? 0.35 ui deterministic jitter at 768 mbps, 1536 mbps, and 3072 mbps refclk = 153.6 mhz pattern = cjpat ? ? 0.17 ? ? 0.17 ? ? 0.17 ? ? 0.17 ui table 1?40. transceiver block jitter specifications for arria ii gx devices (note 1) (part 8 of 10) symbol/ description conditions i3 c4 c5, i5 c6 unit min typ max min typ max min typ max min typ max chapter 1: device datasheet for arria ii devices 1?45 switching characteristics july 2012 altera corporation arria ii device han dbook volume 3: device datasheet and addendum obsai receiver jitter tolerance (12) deterministic jitter tolerance at 768 mbps, 1536 mbps, and 3072 mbps pattern = cjpat > 0.37 > 0.37 > 0.37 > 0.37 ui combined deterministic and random jitter tolerance at 768 mbps, 1536 mbps, and 3072 mbps pattern = cjpat > 0.55 > 0.55 > 0.55 > 0.55 ui sinusoidal jitter tolerance at 768 mbps jitter frequency = 5.4 khz pattern = cjpat > 8.5 > 8.5 > 8.5 > 8.5 ui jitter frequency = 460.8 khz to 20 mhz pattern = cjpat > 0.1 > 0.1 > 0.1 > 0.1 ui sinusoidal jitter tolerance at 1536 mbps jitter frequency = 10.9 khz pattern = cjpat > 8.5 > 8.5 > 8.5 > 8.5 ui jitter frequency = 921.6 khz to 20 mhz pattern = cjpat > 0.1 > 0.1 > 0.1 > 0.1 ui table 1?40. transceiver block jitter specifications for arria ii gx devices (note 1) (part 9 of 10) symbol/ description conditions i3 c4 c5, i5 c6 unit min typ max min typ max min typ max min typ max 1?46 chapter 1: device datasheet for arria ii devices switching characteristics arria ii device handbook volume 3: device datasheet and addendum july 2012 altera corporation table 1?41 lists the transceiver ji tter specifications for all supported protocols for arria ii gz devices. sinusoidal jitter tolerance at 3072 mbps jitter frequency = 21.8 khz pattern = cjpat > 8.5 > 8.5 > 8.5 > 8.5 ui jitter frequency = 1843.2 khz to 20 mhz pattern = cjpat > 0.1 > 0.1 > 0.1 > 0.1 ui notes to table 1?40 : (1) dedicated refclk pins are used to drive the input re ference clocks. the jitter numbers are va lid for the stated conditions only. (2) the jitter numbers for sonet/sdh are compli ant to the gr-253-core issue 3 specification. (3) the jitter numbers for xaui are compli ant to the ieee802.3ae-2002 specification. (4) the jitter numbers for pcie are compli ant to the pcie base specification 2.0. (5) the jitter numbers for srio are comp liant to the rapidio specification 1.3. (6) the jitter numbers for gige are compli ant to the ieee802.3-2002 specification. (7) the jitter numbers for hi gig are compliant to the ie ee802.3ae-2002 specification. (8) the hd-sdi and 3g-sdi jitter numbers are compli ant to the smpte292m and smpte424m specifications. (9) arria ii pcie receivers are compliant to this specification provided the vtx_cm-dc-activ eidle-delta of th e upstream transmit ter is less than 50 mv. (10) the jitter numbers for serial advanced t echnology attachment (sata) are compliant to the serial ata r evision 3.0 specificat ion. (11) the jitter numbers for common public radio interfa ce (cpri) are compliant to the cpri specification v3.0. (12) the jitter numbers for open base station architecture initiative (obsai ) are compliant to the o bsai rp3 specification v4.1. table 1?40. transceiver block jitter specifications for arria ii gx devices (note 1) (part 10 of 10) symbol/ description conditions i3 c4 c5, i5 c6 unit min typ max min typ max min typ max min typ max table 1?41. transceiver block jitter specifications for arria ii gz devices (note 1) , (2) (part 1 of 7) symbol/ description conditions ?c3 and ?i3 ?c4 and ?i4 unit min typ max min typ max sonet/sdh transmit jitter generation (3) peak-to-peak jitter at 622.08 mbps pattern = prbs15 ? ? 0.1 ? ? 0.1 ui rms jitter at 622.08 mbps pattern = prbs15 ? ? 0.01 ? ? 0.01 ui peak-to-peak jitter at 2488.32 mbps pattern = prbs15 ? ? 0.1 ? ? 0.1 ui rms jitter at 2488.32 mbps pattern = prbs15 ? ? 0.01 ? ? 0.01 ui sonet/sdh receiver jitter tolerance (3) jitter tolerance at 622.08 mbps jitter frequency = 0.03 khz pattern = prbs15 > 15 > 15 ui jitter frequency = 25 khz pattern = prbs15 > 1.5 > 1.5 ui jitter frequency = 250 khz pattern = prbs15 > 0.15 > 0.15 ui chapter 1: device datasheet for arria ii devices 1?47 switching characteristics july 2012 altera corporation arria ii device han dbook volume 3: device datasheet and addendum jitter tolerance at 2488.32 mbps jitter frequency = 0.06 khz pattern = prbs15 > 15 > 15 ui jitter frequency = 100 khz pattern = prbs15 > 1.5 > 1.5 ui jitter frequency = 1mhz pattern = prbs15 > 0.15 > 0.15 ui jitter frequency = 10 mhz pattern = prbs15 > 0.15 > 0.15 ui fibre channel transmit jitter generation (4) , (5) total jitter fc-1 pattern = crpat ? ? 0.23 ? ? 0.23 ui deterministic jitter fc-1 pattern = crpat ? ? 0.11 ? ? 0.11 ui total jitter fc-2 pattern = crpat ? ? 0.33 ? ? 0.33 ui deterministic jitter fc-2 pattern = crpat ? ? 0.2 ? ? 0.2 ui total jitter fc-4 pattern = crpat ? ? 0.52 ? ? 0.52 ui deterministic jitter fc-4 pattern = crpat ? ? 0.33 ? ? 0.33 ui fibre channel receiver jitter tolerance (4) , (6) deterministic jitter fc-1 pattern = cjtpat > 0.37 > 0.37 ui random jitter fc-1 pattern = cjtpat > 0.31 > 0.31 ui sinusoidal jitter fc-1 fc/25000 > 1.5 > 1.5 ui fc/1667 > 0.1 > 0.1 ui deterministic jitter fc-2 pattern = cjtpat > 0.33 > 0.33 ui random jitter fc-2 pattern = cjtpat > 0.29 > 0.29 ui sinusoidal jitter fc-2 fc/25000 > 1.5 > 1.5 ui fc/1667 > 0.1 > 0.1 ui deterministic jitter fc-4 pattern = cjtpat > 0.33 > 0.33 ui random jitter fc-4 pattern = cjtpat > 0.29 > 0.29 ui sinusoidal jitter fc-4 fc/25000 > 1.5 > 1.5 ui fc/1667 > 0.1 > 0.1 ui xaui transmit jitter generation (7) total jitter at 3.125 gbps pattern = cjpat ? ? 0.3 ? ? 0.3 ui deterministic jitter at 3.125 gbps pattern = cjpat ? ? 0.17 ? ? 0.17 ui xaui receiver jitter tolerance (7) total jitter ? > 0.65 > 0.65 ui deterministic jitter ? > 0.37 > 0.37 ui table 1?41. transceiver block jitter specifications for arria ii gz devices (note 1) , (2) (part 2 of 7) symbol/ description conditions ?c3 and ?i3 ?c4 and ?i4 unit min typ max min typ max 1?48 chapter 1: device datasheet for arria ii devices switching characteristics arria ii device handbook volume 3: device datasheet and addendum july 2012 altera corporation peak-to-peak jitter jitter frequency = 22.1 khz > 8.5 > 8.5 ui peak-to-peak jitter jitter frequency = 1.875 mhz > 0.1 > 0.1 ui peak-to-peak jitter jitter frequency = 20 mhz > 0.1 > 0.1 ui pcie transmit jitter generation (8) total jitter at 2.5 gbps (gen1)? x1, x4, and x8 compliance pattern ? ? 0.25 ? ? 0.25 ui total jitter at 5 gbps (gen2)? x1, x4, and x8 compliance pattern ? ? 0.25 ? ? ? ui pcie receiver jitter tolerance (8) total jitter at 2.5 gbps (gen1) compliance pattern > 0.6 > 0.6 ui total jitter at 5 gbps (gen2) compliance pattern not supported not supported ui pcie (gen 1) electrical idle detect threshold v rx-idle-detdiffp-p (9) compliance pattern 65 ? 175 65 ? 175 ui srio transmit jitter generation (10) deterministic jitter (peak-to-peak) data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat ? ? 0.17 ? ? 0.17 ui total jitter (peak-to-peak) data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat ? ? 0.35 ? ? 0.35 ui srio receiver jitter tolerance (10) deterministic jitter tolerance (peak-to-peak) data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat > 0.37 > 0.37 ui combined deterministic and random jitter tolerance (peak-to- peak) data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat > 0.55 > 0.55 ui sinusoidal jitter tolerance (peak- to-peak) jitter frequency = 22.1 khz data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat > 8.5 > 8.5 ui jitter frequency = 1.875 mhz data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat > 0.1 > 0.1 ui jitter frequency = 20 mhz data rate = 1.25, 2.5, 3.125 gbps pattern = cjpat > 0.1 > 0.1 ui gige transmit jitter generation (11) deterministic jitter (peak-to-peak) pattern = crpat ? ? 0.14 ? ? 0.14 ui total jitter (peak-to-peak) pattern = crpat ? ? 0.279 ? ? 0.279 ui table 1?41. transceiver block jitter specifications for arria ii gz devices (note 1) , (2) (part 3 of 7) symbol/ description conditions ?c3 and ?i3 ?c4 and ?i4 unit min typ max min typ max chapter 1: device datasheet for arria ii devices 1?49 switching characteristics july 2012 altera corporation arria ii device han dbook volume 3: device datasheet and addendum gige receiver jitter tolerance (11) deterministic jitter tolerance (peak-to-peak) pattern = cjpat > 0.4 > 0.4 ui combined deterministic and random jitter tolerance (peak-to- peak) pattern = cjpat > 0.66 > 0.66 ui higig transmit jitter generation deterministic jitter (peak-to-peak) data rate = 3.75 gbps pattern = cjpat ? ? 0.17 ? ? ? ui total jitter (peak-to-peak) data rate = 3.75 gbps pattern = cjpat ? ? 0.35 ? ? ? ui higig receiver jitter tolerance deterministic jitter tolerance (peak-to-peak) data rate = 3.75 gbps pattern = cjpat > 0.37 ? ? ? ui combined deterministic and random jitter tolerance (peak-to- peak) data rate = 3.75 gbps pattern = cjpat > 0.65 ? ? ? ui sinusoidal jitter tolerance (peak- to-peak) jitter frequency = 22.1 khz data rate = 3.75 gbps pattern = cjpat > 8.5 ? ? ? ui jitter frequency = 22.1 khz data rate = 3.75 gbps pattern = cjpat > 0.1 ? ? ? ui jitter frequency = 22.1 khz data rate = 3.75 gbps pattern = cjpat > 0.1 ? ? ? ui (oif) cei transmitter jitter generation total jitter (peak-to-peak) data rate = 6.375 gbps pattern = prbs15 ber = 10 -12 ?? 0.3 ?? 0.3 ui (oif) cei receiver jitter tolerance deterministic jitter tolerance (peak-to-peak) data rate = 6.375 gbps pattern = prbs31 ber = 10 -12 > 0.675 ? ? ? ui combined deterministic and random jitter tolerance (peak-to- peak) data rate = 6.375 gbps pattern = prbs31 ber = 10 -12 > 0.988 ? ? ? ui table 1?41. transceiver block jitter specifications for arria ii gz devices (note 1) , (2) (part 4 of 7) symbol/ description conditions ?c3 and ?i3 ?c4 and ?i4 unit min typ max min typ max 1?50 chapter 1: device datasheet for arria ii devices switching characteristics arria ii device handbook volume 3: device datasheet and addendum july 2012 altera corporation sinusoidal jitter tolerance (peak- to-peak) jitter frequency = 38.2 khz data rate = 6.375 gbps pattern = prbs31 ber = 10 -12 > 0.5 ? ? ? ui jitter frequency = 3.82 mhz data rate = 6.375 gbps pattern = prbs31 ber = 10 -12 > 0.05 ? ? ? ui jitter frequency = 20 mhz data rate = 6.375 gbps pattern = prbs31 ber = 10 -12 > 0.05 ? ? ? ui sdi transmitter jitter generation (12) alignment jitter (peak-to-peak) data rate = 1.485 gbps (hd) pattern = color bar low-frequency roll-off = 100 khz 0.2 ? ? 0.2 ? ? ui data rate = 2.97 gbps (3g) pattern = color bar low-frequency roll-off = 100 khz 0.3 ? ? 0.3 ? ? ui sdi receiver jitter tolerance (12) sinusoidal jitter tolerance (peak- to-peak) jitter frequency = 15 khz data rate = 2.97 gbps (3g) pattern = single line scramble color bar > 2 > 2 ui jitter frequency = 100 khz data rate = 2.97 gbps (3g) pattern = single line scramble color bar > 0.3 > 0.3 ui jitter frequency = 148.5 mhz data rate = 2.97 gbps (3g) pattern = single line scramble color bar > 0.3 > 0.3 ui sinusoidal jitter tolerance (peak- to-peak) jitter frequency = 20 khz data rate = 1.485 gbps (hd) pattern = 75% color bar > 1 > 1 ui jitter frequency = 100 khz data rate = 1.485 gbps (hd) pattern = 75% color bar > 0.2 > 0.2 ui jitter frequency = 148.5 mhz data rate = 1.485 gbps (hd) pattern = 75% color bar > 0.2 > 0.2 ui sas transmit jitter generation (13) total jitter at 1.5 gbps (g1) pattern = cjpat ? ? 0.55 ? ? 0.55 ui deterministic jitter at 1.5 gbps (g1) pattern = cjpat ? ? 0.35 ? ? 0.35 ui total jitter at 3.0 gbps (g2) pattern = cjpat ? ? 0.55 ? ? 0.55 ui table 1?41. transceiver block jitter specifications for arria ii gz devices (note 1) , (2) (part 5 of 7) symbol/ description conditions ?c3 and ?i3 ?c4 and ?i4 unit min typ max min typ max chapter 1: device datasheet for arria ii devices 1?51 switching characteristics july 2012 altera corporation arria ii device han dbook volume 3: device datasheet and addendum deterministic jitter at 3.0 gbps (g2) pattern = cjpat ? ? 0.35 ? ? 0.35 ui total jitter at 6.0 gbps (g3) pattern = cjpat ? ? 0.25 ? ? 0.25 ui random jitter at 6.0 gbps (g3) pattern = cjpat ? ? 0.15 ? ? 0.15 ui sas receiver jitter tolerance (13) total jitter tolerance at 1.5 gbps (g1) pattern = cjpat ? ? 0.65 ? ? 0.65 ui deterministic jitter tolerance at 1.5 gbps (g1) pattern = cjpat ? ? 0.35 ? ? 0.35 ui sinusoidal jitter tolerance at 1.5 gbps (g1) jitter frequency = 900 khz to 5 mhz pattern = cjtpat ber = 1e-12 > 0.1 > 0.1 ui cpri transmit jitter generation (14) total jitter e.6.hv, e.12.hv pattern = cjpat ? ? 0.279 ? ? 0.279 ui e.6.lv, e.12.lv, e.24.lv, e.30.lv pattern = cjpat ? ? 0.35 ? ? 0.35 ui deterministic jitter e.6.hv, e.12.hv pattern = cjpat ? ? 0.14 ? ? 0.14 ui e.6.lv, e.12.lv, e.24.lv, e.30.lv pattern = cjpat ? ? 0.17 ? ? 0.17 ui cpri receiver jitter tolerance (14) total jitter tolerance e.6.hv, e.12.hv pattern = cjpat > 0.66 > 0.66 ui deterministic jitter tolerance e.6.hv, e.12.hv pattern = cjpat > 0.4 > 0.4 ui total jitter tolerance e.6.lv, e.12.lv, e.24.lv, e.30.lv pattern = cjpat > 0.65 > 0.65 ui deterministic jitter tolerance e.6.lv, e.12.lv, e.24.lv, e.30.lv pattern = cjpat > 0.37 > 0.37 ui combined deterministic and random jitter tolerance e.6.lv, e.12.lv, e.24.lv, e.30.lv pattern = cjpat > 0.55 > 0.55 ui obsai transmit jitter generation (15) total jitter at 768 mbps, 1536 mbps, and 3072 mbps refclk = 153.6 mhz pattern cjpat ? ? 0.35 ? ? 0.35 ui deterministic jitter at 768 mbps, 1536 mbps, and 3072 mbps refclk = 153.6 mhz pattern cjpat ? ? 0.17 ? ? 0.17 ui table 1?41. transceiver block jitter specifications for arria ii gz devices (note 1) , (2) (part 6 of 7) symbol/ description conditions ?c3 and ?i3 ?c4 and ?i4 unit min typ max min typ max 1?52 chapter 1: device datasheet for arria ii devices switching characteristics arria ii device handbook volume 3: device datasheet and addendum july 2012 altera corporation obsai receiver jitter tolerance (15) deterministic jitter tolerance at 768 mbps, 1536 mbps, and 3072 mbps pattern = cjpat > 0.37 > 0.37 ui combined deterministic and random jitter tolerance at 768 mbps, 1536 mbps, and 3072 mbps pattern = cjpat > 0.55 > 0.55 ui sinusoidal jitter tolerance at 768 mbps jitter frequency = 5.4 khz pattern = cjpat > 8.5 > 8.5 ui jitter frequency = 460 mhz to 20 mhz pattern = cjpat > 0.1 > 0.1 ui sinusoidal jitter tolerance at 1536 mbps jitter frequency = 10.9 khz pattern = cjpat > 8.5 > 8.5 ui jitter frequency = 921.6 mhz to 20 mhz pattern = cjpat > 0.1 > 0.1 ui sinusoidal jitter tolerance at 3072 mbps jitter frequency = 21.8 khz pattern = cjpat > 8.5 > 8.5 ui jitter frequency = 1843.2 mhz to 20 mhz pattern = cjpat > 0.1 > 0.1 ui notes to table 1?41 : (1) dedicated refclk pins were used to dri ve the input reference clocks. (2) the jitter numbers are valid for the stated conditions only. (3) the jitter numbers for sonet/sdh are compli ant to the gr-253-core issue 3 specification. (4) the jitter numbers for fibre ch annel are compliant to the fc-pi-4 specification revision 6.10. (5) the fibre channel transmitter jitter generation numbers are comp liant to the specification at the ? t inter operability point. (6) the fibre channel receiver jitte r tolerance numbers are complian t to the specification at the ? r interpretability point. (7) the jitter numbers for xaui are compli ant to the ieee802.3ae-2002 specification. (8) the jitter numbers for pcie are compli ant to the pcie base specification 2.0. (9) arria ii gz pcie receivers are compliant to this specificat ion provided the v tx-cm-dc-activeidle-delta of the upstream transmi tter is less than 50 mv. (10) the jitter numbers for srio are comp liant to the rapidio specification 1.3. (11) the jitter numbers for gige are compli ant to the ieee802.3-2002 specification. (12) the hd-sdi and 3g-sdi jitter numbers are compli ant to the smpte292m and smpte424m specifications. (13) the jitter numbers fo r serial attached scsi (sas) are co mpliant to the sas -2.1 specification. (14) the jitter numbers for cpri are comp liant to the cpri specification v3.0. (15) the jitter numbers for obsai are compliant to th e obsai rp3 specification v4.1. table 1?41. transceiver block jitter specifications for arria ii gz devices (note 1) , (2) (part 7 of 7) symbol/ description conditions ?c3 and ?i3 ?c4 and ?i4 unit min typ max min typ max chapter 1: device datasheet for arria ii devices 1?53 switching characteristics july 2012 altera corporation arria ii device han dbook volume 3: device datasheet and addendum core performance specifications for the arria ii device family this section describes the clock tree, phase-locked loop (pll), digital signal processing (dsp), embedded memory, config uration, and jtag specifications for arria ii gx and gz devices. clock tree specifications table 1?42 lists the clock tree specifications for arria ii gx devices. table 1?43 lists the clock tree specifications for arria ii gz devices. pll specifications table 1?44 lists the pll specifications for arria ii gx devices. table 1?42. clock tree performance for arria ii gx devices clock network performance unit i3, c4 c5,i5 c6 gclk and rclk 500 500 400 mhz pclk 420 350 280 mhz table 1?43. clock tree performance for arria ii gz devices clock network performance unit ?c3 and ?i3 ?c4 and ?i4 gclk and rclk 700 500 mhz pclk 500 450 mhz table 1?44. pll specifications for arria ii gx devices (part 1 of 3) symbol description min typ max unit f in input clock frequency (from clock input pins residing in right/top/bottom banks) (?4 speed grade) 5 ? 670 (1) mhz input clock frequency (from clock input pins residing in right/top/bottom banks) (?5 speed grade) 5 ? 622 (1) mhz input clock frequency (from clock input pins residing in right/top/bottom banks) (?6 speed grade) 5 ? 500 (1) mhz f inpfd input frequency to the pfd 5 ? 325 mhz f vco pll vco operating range (2) 600 ? 1,400 mhz f induty input clock duty cycle 40 ? 60 % f einduty external feedback clock input duty cycle 40 ? 60 % t inccj (3) , (4) input clock cycle-to-cycle jitter (frequency ? 100 mhz) ? ? 0.15 ui (p?p) input clock cycle-to-cycle jitter (frequency ? 100 mhz) ? ? 750 ps (p?p) 1?54 chapter 1: device datasheet for arria ii devices switching characteristics arria ii device handbook volume 3: device datasheet and addendum july 2012 altera corporation f out output frequency for internal global or regional clock (?4 speed grade) ? ? 500 mhz output frequency for internal global or regional clock (?5 speed grade) ? ? 500 mhz output frequency for internal global or regional clock (?6 speed grade) ? ? 400 mhz f out_ext output frequency for external clock output (?4 speed grade) ? ? 670 (5) mhz output frequency for external clock output (?5 speed grade) ? ? 622 (5) mhz output frequency for external clock output (?6 speed grade) ? ? 500 (5) mhz t outduty duty cycle for external clock output (when set to 50%) 45 50 55 % t outpj_dc dedicated clock output period jitter (f out ? 100 mhz) ? ? 300 ps (p?p) dedicated clock output period jitter (f out ? 100 mhz) ? ? 30 mui (p?p) t outccj_dc dedicated clock output cycle-to-cycle jitter (f out ? 100 mhz) ? ? 300 ps (p?p) dedicated clock output cycle-to-cycle jitter (f out ? 100 mhz) ? ? 30 mui (p?p) f outpj_io regular i/o clock output period jitter (f out ? 100 mhz) ? ? 650 ps (p?p) regular i/o clock output period jitter (f out ? 100 mhz) ? ? 65 mui (p?p) f outccj_io regular i/o clock output cycle-to-cycle jitter (f out ? 100 mhz) ? ? 650 ps (p?p) regular i/o clock output cycle-to-cycle jitter (f out ? 100 mhz) ? ? 65 mui (p?p) t configpll time required to reconfigure pll scan chains ? 3.5 ? scanclk cycles t configphase time required to reconfigure phase shift ? 1 ? scanclk cycles f scanclk scanclk frequency ? ? 100 mhz t lock time required to lock from end of device configuration ? ? 1 ms t dlock time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) ?? 1 ms f cl b w pll closed-loop low bandwidth ? 0.3 ? mhz pll closed-loop medium bandwidth ? 1.5 ? mhz pll closed-loop high bandwidth ? 4 ? mhz t pll_pserr accuracy of pll phase shift ? ? 50 ps t areset minimum pulse width on areset signal 10 ? ? ns table 1?44. pll specifications for arria ii gx devices (part 2 of 3) symbol description min typ max unit chapter 1: device datasheet for arria ii devices 1?55 switching characteristics july 2012 altera corporation arria ii device han dbook volume 3: device datasheet and addendum table 1?45 lists the pll specifications for arria ii gz devices when operating in both the commercial junction temperature range (0 to 85c) and the industrial junction temperature range (-40 to 100c). t casc_ outjitter_ period_ dedclk (6) , (7) period jitter for dedicated clock output in cascaded plls (fout ? 100 mhz) ? ? 425 ps (p-p) period jitter for dedicated clock output in cascaded plls (fout ? 100 mhz) ? ? 42.5 mui (p-p) notes to table 1?44 : (1) f in is limited by the i/o f max . (2) the vco frequency reported by the qu artus ii software in the pll summary section of the compila tion report takes into consid eration the vco post-scale counter k value. therefore, if the counter k has a va lue of 2, the frequency report ed can be lower than the f vco specification. (3) a high-input jitter directly affects the pll output jitter. to have low pll outpu t clock jitter, you must provide a clean-cl ock source, which is less than 200 ps. (4) f ref is fin/n when n = 1. (5) this specification is limited by the lower of the two: i/o f max or f out of the pll. (6) peak-to-peak jitter with a probability level of 10 ?12 (14 sigma, 99.99999 999974404% conf idence level). the output jitter specification applies to the intrinsic jitter of the pll, when an input jitter of 30 ps is applied. th e external memory interf ace clock output jitter specifications use a different measurement met hod and are available in table 1?62 on page 1?70 . (7) the cascaded pll specification is only applicable with the following condition: a. upstream pll: 0.59 mhz ?? upstream pll bw < 1 mhz b. downstream pll: downstream pll bw > 2 mhz table 1?44. pll specifications for arria ii gx devices (part 3 of 3) symbol description min typ max unit table 1?45. pll specifications for arria ii gz devices (part 1 of 2) symbol parameter min typ max unit f in input clock frequency (?3 speed grade) 5 ? 717 (1) mhz input clock frequency (?4 speed grade) 5 ? 717 (1) mhz f inpfd input frequency to the pfd 5 ? 325 mhz f vco pll vco operating range (?3 speed grade) 600 ? 1,300 mhz pll vco operating range (?4 speed grade) 600 ? 1,300 mhz t einduty input clock or external feedback clock input duty cycle 40 ? 60 % f out output frequency for internal global or regional clock (?3 speed grade) ? ? 700 (2) mhz output frequency for internal global or regional clock (?4 speed grade) ? ? 500 (2) mhz f out_ext output frequency for external clock output (?3 speed grade) ? ? 717 (2) mhz output frequency for external clock output (?4 speed grade) ? ? 717 (2) mhz t outduty duty cycle for external clock output (when set to 50%) 45 50 55 % t fcomp external feedback clock compensation time ? ? 10 ns t configpll time required to reconfigure scan chain ? 3.5 ? scanclk cycles t configphase time required to reconfigure phase shift ? 1 ? scanclk cycles f scanclk scanclk frequency ? ? 100 mhz t lock time required to lock from end-of-device configuration or de-assertion of areset ?? 1 ms 1?56 chapter 1: device datasheet for arria ii devices switching characteristics arria ii device handbook volume 3: device datasheet and addendum july 2012 altera corporation t dlock time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) ?? 1 ms f clbw pll closed-loop low bandwidth ? 0.3 ? mhz pll closed-loop medium bandwidth ? 1.5 ? mhz pll closed-loop high bandwidth (7) ?4 ? mhz t pll_pserr accuracy of pll phase shift ? ? 50 ps t areset minimum pulse width on the areset signal 10 ? ? ns t inccj (3) , (4) input clock cycle to cycle jitter (f ref 100 mhz) ? ? 0.15 ui (p-p) input clock cycle to cycle jitter (f ref < 100 mhz) ? ? 750 ps (p-p) t outpj_dc (5) period jitter for dedicated clock output (f out 100 mhz) ? ? 175 ps (p-p) period jitter for dedicated clock output (f out < 100 mhz) ? ? 17.5 mui (p-p) t outccj_dc (5) cycle to cycle jitter for dedicated clock output (f out 100 mhz) ? ? 175 ps (p-p) cycle to cycle jitter for dedicated clock output (f out < 100 mhz) ? ? 17.5 mui (p-p) t outpj_io (5) , (8) period jitter for clock output on regular i/o (f out 100 mhz) ? ? 600 ps (p-p) period jitter for clock output on regular i/o (f out < 100 mhz) ? ? 60 mui (p-p) t outccj_io (5) , (8) cycle to cycle jitter for clock output on regular i/o (f out 100 mhz) ? ? 600 ps (p-p) cycle to cycle jitter for clock output on regular i/o (f out < 100 mhz) ? ? 60 mui (p-p) t casc_outpj_dc (5) , (6) period jitter for dedicated clock output in cascaded plls (f out 100mhz) ? ? 250 ps (p-p) period jitter for dedicated clock output in cascaded plls (f out < 100mhz) ? ? 25 mui (p-p) f drift frequency drift after pfdena is disabled for duration of 100 us ? ? 10 % notes to table 1?45 : (1) this specification is limited in the qu artus ii software by the i/o m aximum frequency. the maximu m i/o frequency is differen t for each i/o standard. (2) this specification is limited by the lower of the two: i/o f max or f out of the pll. (3) a high input jitter directly affects th e pll output jitter. to have low pll output clock jitter, you must provide a clean cl ock source that is less than 120 ps. (4) f ref is fin/n when n = 1. (5) peak-to-peak jitter with a probability level of 10 ?12 (14 sigma, 99.99999999974404% confidence level). the output jitter specification applies to the intrinsic jitter of the p ll, when an input jitter of 30 ps is applied. the external memo ry interface clock output jitter specifications use a different measurement met hod and are available in table 1?64 on page 1?71 . (6) the cascaded pll specification is only applicable with the following condition: a. upstream pll: 0.59 mhz ? upstream pll bw < 1 mhz b. downstream pll: downstream pll bw > 2 mhz (7) high bandwidth pll settings are not supported in external feedback mode. (8) external memory interface clock output jitter specifications use a different m easurement method, which is available in table 1?63 on page 1?71 . table 1?45. pll specifications for arria ii gz devices (part 2 of 2) symbol parameter min typ max unit chapter 1: device datasheet for arria ii devices 1?57 switching characteristics july 2012 altera corporation arria ii device han dbook volume 3: device datasheet and addendum dsp block specifications table 1?46 lists the dsp block performance sp ecifications for arria ii gx devices. table 1?47 lists the dsp block performance spec ifications for arria ii gz devices. table 1?46. dsp block performance specifications for arria ii gx devices (note 1) mode resources used performance unit number of multipliers c4 i3 c5,i5 c6 9 9-bit multiplier 1 380 310 300 250 mhz 12 12-bit multiplier 1 380 310 300 250 mhz 18 18-bit multiplier 1 380 310 300 250 mhz 36 36-bit multiplier 1 350 270 270 220 mhz 18 36-bit high-precision multiplier adder mode 1 350 270 270 220 mhz 18 18-bit multiply accumulator 4 380 310 300 250 mhz 18 18-bit multiply adder 4 380 310 300 250 mhz 18 18-bit multiply adder-signed full precision 2 380 310 300 250 mhz 18 18-bit multiply adder with loopback (2) 2 275 220 220 180 mhz 36-bit shift (32-bit data) 1 350 270 270 220 mhz double mode 1 350 270 270 220 mhz notes to table 1?46 : (1) maximum is for a full y-pipelined block with round and saturation disabled. (2) maximum is for loopback input registers disabled, round and saturation disabled, pipeline and output registers enabled. table 1?47. dsp block performance specifications for arria ii gz devices (note 1) (part 1 of 2) mode resources used performance unit number of multipliers ?3 ?4 9 9-bit multiplier 1 460 400 mhz 12 12-bit multiplier 1 500 440 mhz 18 18-bit multiplier 1 550 480 mhz 36 36-bit multiplier 1 440 380 mhz 18 18-bit multiply accumulator 4 440 380 mhz 18 18-bit multiply adder 4 470 410 mhz 18 18-bit multiply adder-signed full precision 2 450 390 mhz 18 18-bit multiply adder with loopback (2) 2 350 310 mhz 36-bit shift (32-bit data) 1 440 380 mhz 1?58 chapter 1: device datasheet for arria ii devices switching characteristics arria ii device handbook volume 3: device datasheet and addendum july 2012 altera corporation embedded memory block specifications table 1?48 lists the embedded memory block specifications for arria ii gx devices. double mode 1 440 380 mhz notes to table 1?47 : (1) maximum is for fully pipelined block with round and saturation disabled. (2) maximum for loopback in put registers disabled, round and saturation disabled, and pipeline and output registers enabled. table 1?47. dsp block performance specifications for arria ii gz devices (note 1) (part 2 of 2) mode resources used performance unit number of multipliers ?3 ?4 table 1?48. embedded memory block performance specifications for arria ii gx devices memory mode resources used performance unit aluts embedded memory i3 c4 c5,i5 c6 memory logic array block (mlab) single port 64 10 0 1 450 500 450 378 mhz simple dual-port 32 20 single clock 0 1 270 500 450 378 mhz simple dual-port 64 10 single clock 0 1 428 500 450 378 mhz m9k block single-port 256 36 0 1 360 400 360 310 mhz single-port 256 36, with the read-during-write option set to old data 0 1 250 280 250 210 mhz simple dual-port 256 36 single clk 0 1 360 400 360 310 mhz single-port 256 36 single clk, with the read-during-write option set to old data 0 1 250 280 250 210 mhz true dual port 512 18 single clk 0 1 360 400 360 310 mhz true dual-port 512 18 single clk, with the read-during-write option set to old data 0 1 250 280 250 210 mhz min pulse width (clock high time) ? ? 900 850 950 1130 ps min pulse width (clock low time) ? ? 730 690 770 920 ps chapter 1: device datasheet for arria ii devices 1?59 switching characteristics july 2012 altera corporation arria ii device han dbook volume 3: device datasheet and addendum table 1?49 lists the embedded memory block specifications for arria ii gz devices. table 1?49. embedded memory block performance specifications for arria ii gz devices (note 1) memory mode resources used performance unit aluts trimatrix memory c3 i3 c4 i4 mlab (2) single port 64 10 0 1 500 500 450 450 mhz simple dual-port 32 20 0 1 500 500 450 450 mhz simple dual-port 64 10 0 1 500 500 450 450 mhz rom 64 10 0 1 500 500 450 450 mhz rom 32 20 0 1 500 500 450 450 mhz m9k block (2) single-port 256 36 0 1 540 540 475 475 mhz simple dual-port 256 36 0 1 490 490 420 420 mhz simple dual-port 256 36, with the read-during-write option set to old data 0 1 340 340 300 300 mhz true dual port 512 18 0 1 430 430 370 370 mhz true dual-port 512 18, with the read-during-write option set to old data 0 1 335 335 290 290 mhz rom 1 port 0 1 540 540 475 475 mhz rom 2 port 0 1 540 540 475 475 mhz min pulse width (clock high time) ? ? 800 800 850 850 ps min pulse width (clock low time) ? ? 625 625 690 690 ps m144k block (2) single-port 2k 72 0 1 440 400 380 350 mhz simple dual-port 2k 72 0 1 435 375 385 325 mhz simple dual-port 2k 72, with the read-during-write option set to old data 0 1 240 225 205 200 mhz simple dual-port 2k 64 (with ecc) 0 1 300 295 255 250 mhz true dual-port 4k 36 0 1 375 350 330 310 mhz true dual-port 4k 36, with the read-during-write option set to old data 0 1 230 225 205 200 mhz rom 1 port 0 1 500 450 435 420 mhz rom 2 port 0 1 465 425 400 400 mhz min pulse width (clock high time) ? ? 755 860 860 950 ps min pulse width (clock low time) ? ? 625 690 690 690 ps notes to table 1?48 : (1) to achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on -chip pll set to 50% output duty cycle. use the quartu s ii software to report timi ng for this and other memo ry block clo cking schemes. (2) when you use the error detection crc f eature, there is no degradation in f max . 1?60 chapter 1: device datasheet for arria ii devices switching characteristics arria ii device handbook volume 3: device datasheet and addendum july 2012 altera corporation configuration table 1?50 lists the configuration mode specifications for arria ii gx and gz devices. jtag specifications table 1?51 lists the jtag timing parameters and values for arria ii gx and gz devices. chip-wide reset (dev_clrn) specifications table 1?52 lists the specifications for the chip-wide reset ( dev_clrn ) for arria ii gx and gz devices. table 1?50. configuration mode specifications for arria ii devices programming mode dclk frequency unit min typ max passive serial ? ? 125 mhz fast passive parallel ? ? 125 mhz fast active serial (fast clock) 17 26 40 mhz fast active serial (slow clock) 8.5 13 20 mhz remote update only in fast as mode ? ? 10 mhz table 1?51. jtag timing parameters and values for arria ii devices symbol description min max unit t jcp tck clock period 30 ? ns t jch tck clock high time 14 ? ns t jcl tck clock low time 14 ? ns t jpsu (tdi) tdi jtag port setup time 1 ? ns t jpsu (tms) tms jtag port setup time 3 ? ns t jph jtag port hold time 5 ? ns t jpco jtag port clock to output ? 11 ns t jpzx jtag port high impedance to valid output ? 14 ns t jpxz jtag port valid output to high impedance ? 14 ns table 1?52. chip-wide reset (dev_clrn) specifications for arria ii devices description min typ max unit dev_clrn 500 ? ? ? s chapter 1: device datasheet for arria ii devices 1?61 switching characteristics july 2012 altera corporation arria ii device han dbook volume 3: device datasheet and addendum periphery performance this section describes periphery performanc e, including high-speed i/o, external memory interface, and ioe programmable delay. i/o performance supports several system in terfaces, for example the high-speed i/o interface, external memory interface, an d the pci/pci-x bus interface. i/o using sstl-18 class i termination standard ca n achieve up to the stated ddr2 sdram interfacing speed with typical ddr2 sdra m memory interface setup. i/o using general purpose i/o (gpio) standards such as 3.0, 2.5, 1.8, or 1.5 lvttl/lvcmos are capable of typical 200 mhz interfacing frequency with 10pf load. 1 actual achievable frequency depends on design- and system-specific factors. you should perform hspice/ibis simulations base d on your specific design and system setup to determine the maximum achievable frequency in your system. high-speed i/o specification table 1?53 lists the high-speed i/o timing for arria ii gx devices. table 1?53. high-speed i/o specifications for arria ii gx devices (part 1 of 4) symbol conditions i3 c4 c5,i5 c6 unit min max min max min max min max clock f hsclk_in (input clock frequency)?row i/o clock boost factor, w = 1 to 40 (1) 5 670 5 670 5 622 5 500 mhz f hsclk_in (input clock frequency)? column i/o clock boost factor, w = 1 to 40 (1) 5 500 5 500 5 472.5 5 472.5 mhz f hsclk_out (output clock frequency)?row i/o ? 5 670 5 670 5 622 5 500 mhz f hsclk_out (output clock frequency)? column i/o ? 5 500 5 500 5 472.5 5 472.5 mhz 1?62 chapter 1: device datasheet for arria ii devices switching characteristics arria ii device handbook volume 3: device datasheet and addendum july 2012 altera corporation transmitter f hsdr_tx (true lvds output data rate) serdes factor, j = 3 to 10 (using dedicated serdes) 150 1250 (2) 150 1250 (2) 150 1050 (2) 150 840 mbps serdes factor, j = 4 to 10 (using logic elements as serdes) (3) 945 (3) 945 (3) 840 (3) 740 mbps serdes factor, j = 2 (using ddr registers) and j = 1 (using sdr register) (3) (3) (3) (3) (3) (3) (3) (3) mbps f hsdr_tx_e3r (emulated lvds_e_3r output data rate) (7) serdes factor, j = 4 to 10 (3) 945 (3) 945 (3) 840 (3) 740 mbps table 1?53. high-speed i/o specifications for arria ii gx devices (part 2 of 4) symbol conditions i3 c4 c5,i5 c6 unit min max min max min max min max chapter 1: device datasheet for arria ii devices 1?63 switching characteristics july 2012 altera corporation arria ii device han dbook volume 3: device datasheet and addendum t tx_jitter (4) true lvds with dedicated serdes (data rate 600?1,250 mbps) ? 175 ? 175 ? 225 ? 300 ps true lvds with dedicated serdes (data rate < 600 mbps) ? 0.105 ? 0.105 ? 0.135 ? 0.18 ui true lvds and emulated lvds_e_3r with logic elements as serdes (data rate 600 ? 945 mbps) ? 260 ? 260 ? 300 ? 350 ps true lvds and emulated lvds_e_3r with logic elements as serdes (data rate < 600 mbps) ? 0.16 ? 0.16 ? 0.18 ? 0.21 ui t tx_dcd true lvds and emulated lvds_e_3r 45 55 45 55 45 55 45 55 % t rise and t fall true lvds and emulated lvds_e_3r ? 200 ? 200 ? 225 ? 250 ps tccs true lvds (5) ? 150 ? 150 ? 175 ? 200 ps emulated lvds_e_3r ? 200 ? 200 ? 250 ? 300 ps receiver (6) true differential i/o standards - f hsdrdpa (data rate) serdes factor j = 3 to 10 150 1250 150 1250 150 1050 150 840 mbps table 1?53. high-speed i/o specifications for arria ii gx devices (part 3 of 4) symbol conditions i3 c4 c5,i5 c6 unit min max min max min max min max 1?64 chapter 1: device datasheet for arria ii devices switching characteristics arria ii device handbook volume 3: device datasheet and addendum july 2012 altera corporation table 1?54 lists the high-speed i/o timing for arria ii gz devices. f hsdr (data rate) serdes factor j = 3 to 10 (3) 945 (7) (3) 945 (7) (3) 740 (7) (3) 640 (7) mbps serdes factor j = 2 (using ddr registers) (3) (7) (3) (7) (3) (7) (3) (7) mbps serdes factor j = 1 (using sdr registers) (3) (7) (3) (7) (3) (7) (3) (7) mbps soft-cdr ppm tolerance soft-cdr mode ? 300 ? 300 ? 300 ? 300 ? ppm dpa run length dpa mode ? 10,000 ? 10,000 ? 10,000 ? 10,000 ui sampling window (sw) non-dpa mode (5) ? 300 ? 300 ? 350 ? 400 ps notes to table 1?53 : (1) f hsclk_in = f hsdr / w. use w to determine the supported selection of input reference clock frequencies for the desired data rate. (2) applicable for interfacing wi th dpa receivers only. for interf acing with non-dpa receivers, you must calculate the leftover timing margin in the receiver by performing link timi ng closure analysis. for arria ii gx transmitter to arria ii gx non-dpa receiver, the maximum s upported data rate is 945 mbps. for data rates above 840 mbps, perform pcb tr ace compensation by ad justing the pcb trace length for lvds chan nels to improve channel-to-channel skews. (3) the minimum and maximum specif ication depends on the clock source (for example, pll and clock pin) and the clock routing res ource you use (global, regional, or local). the i/o differential buffe r and input register do not have a minimum toggle rate. (4) the specification is only applicab le under the influence of core noise. (5) applicable for true lvds using dedicated serdes only. (6) dedicated serdes and dpa features are only available on the right banks. (7) you must calculate the leftover timing margin in the receiver by performing li nk timing closure analys is. you must consider the board skew margin, transmitter channel-to -channel skew, and the receiver sampling margin to determin e the leftover timing margin. table 1?53. high-speed i/o specifications for arria ii gx devices (part 4 of 4) symbol conditions i3 c4 c5,i5 c6 unit min max min max min max min max table 1?54. high-speed i/o specifications for arria ii gz devices (note 1), (2), (10) (part 1 of 3) symbol conditions c3, i3 c4, i4 unit min typ max min typ max clock f hsclk_in (input clock frequency) true differential i/o standards clock boost factor w = 1 to 40 (3) 5 ? 717 5 ? 717 mhz f hsclk_in (input clock frequency) single ended i/o standards (9) clock boost factor w = 1 to 40 (3) 5 ? 717 5 ? 717 mhz f hsclk_in (input clock frequency) single ended i/o standards (10) clock boost factor w = 1 to 40 (3) 5 ? 420 5 ? 420 mhz chapter 1: device datasheet for arria ii devices 1?65 switching characteristics july 2012 altera corporation arria ii device han dbook volume 3: device datasheet and addendum f hsclk_out (output clock frequency) ? 5 ? 717 (7) 5 ? 717 (7) mhz transmitter f hsdr (true lvds output data rate) serdes factor, j = 3 to 10 (using dedicated serdes) (8) (4) ? 1250 (4) ? 1250 mbps serdes factor j = 2, (using ddr registers) (4) ? (5) (4) ? (5) mbps serdes factor j = 1, (uses an sdr register) (4) ? (5) (4) ? (5) mbps f hsdr (emulated lvds_e_3r output data rate) (5) serdes factor j = 4 to 10 (4) ? 1152 (4) ? 800 mbps f hsdr (emulated lvds_e_1r output data rate) (4) ?200 (4) ? 200 mbps t x jitter total jitter for data rate, 600 mbps to 1.6 gbps ??160??160ps total jitter for data rate, < 600 mbps ??0.1??0.1ui t x jitter - emulated differential i/o standards with three external output resistor network total jitter for data rate, 600 mbps to 1.25 gbps ??300??325ps total jitter for data rate < 600 mbps ? ? 0.2 ? ? 0.25 ui t x jitter - emulated differential i/o standards with one external output resistor network ? ??0.15??0.15ui t duty tx output clock duty cycle for both true and emulated differential i/o standards 45 50 55 45 50 55 % table 1?54. high-speed i/o specifications for arria ii gz devices (note 1), (2), (10) (part 2 of 3) symbol conditions c3, i3 c4, i4 unit min typ max min typ max 1?66 chapter 1: device datasheet for arria ii devices switching characteristics arria ii device handbook volume 3: device datasheet and addendum july 2012 altera corporation table 1?55 lists dpa lock time specifications for arria ii gx and gz devices. t rise & t fall true differential i/o standards ??200??200ps emulated differential i/o standards with three external output resistor networks ??250??300ps emulated differential i/o standards with one external output resistor ??500??500ps tccs true lvds ? ? 100 ? ? 100 ps emulated lvds_e_3r ??250??250ps receiver true differential i/o standards - f hsdrdpa (data rate) serdes factor j = 3 to 10 150 ? 1250 150 ? 1250 mbps f hsdr (data rate) serdes factor j = 3 to 10 (4) ? (6) (4) ? (6) mbps serdes factor j = 2, uses ddr registers (4) ? (5) (4) ? (5) mbps serdes factor j = 1, uses an sdr register (4) ? (5) (4) ? (5) mbps dpa run length dpa mode ? ? 10000 ? ? 10000 ui soft-cdr ppm tolerance soft-cdr mode ? ? 300 ? ? 300 ppm sampling window (sw) non-dpa mode ? ? 300 ? ? 300 ps notes to table 1?54 : (1) when j = 3 to 10, use the serdes block. (2) when j = 1 or 2, bypass the serdes block. (3) clock boost factor (w) is the ratio between input data rate to the input clock rate. (4) the minimum specification depends on th e clock source (for example, the pll and cl ock pin) and the clock routing resource (g lobal, regional, or local) that you use. the i/o differential buffer an d input register do not have a minimum toggle rate. (5) you must calculate the leftover timing margin in the receiver by performing li nk timing closure analys is. you must consider the board skew margin, transmitter channel-to-channel skew, and receiver sampling margin to determine leftover timing margin. (6) you can estimate the achievable maximum data rate for non-dpa mode by perfor ming link timing closure analysis. you must cons ider the board skew margin, transmitter delay ma rgin, and the receiver sampling margin to determine the maximum data rate supported. (7) this is achieved by using th e lvds and dpa clock network. (8) if the receiver with dpa enabled an d transmitter are using shared plls, the minimum data rate is 150 mbps. (9) this only applies to dpa and soft-cdr modes. (10) this only applies to lv ds source synchronous mode. table 1?54. high-speed i/o specifications for arria ii gz devices (note 1), (2), (10) (part 3 of 3) symbol conditions c3, i3 c4, i4 unit min typ max min typ max chapter 1: device datasheet for arria ii devices 1?67 switching characteristics july 2012 altera corporation arria ii device han dbook volume 3: device datasheet and addendum figure 1?5 shows the lvds soft-cdr/dpa sinusoidal jitter tolerance specification for arria ii gz devices at a data rate less than 1.25 gbps and all the arria ii gx devices. table 1?55. dpa lock time specifications for arria ii devices (note 1) , (2) , (3) standard training pattern number of data transitions in one repetition of the training pattern number of repetitions per 256 data transitions (4) maximum spi-4 00000000001111111111 2 128 640 data transitions parallel rapid i/o 00001111 2 128 640 data transitions 10010000 4 64 640 data transitions miscellaneous 10101010 8 32 640 data transitions 01010101 8 32 640 data transitions notes to table 1?55 : (1) the dpa lock time is for one channel. (2) one data transition is defined as a 0-to-1 or 1-to-0 transition. (3) the dpa lock time stated in the table applie s to both commercial and industrial grade. (4) this is the number of repetition s for the stated training pattern to achieve the 256 data transitions. figure 1?5. lvds soft-cdr/dpa sinusoidal jitter tolerance specification for all arria ii gx devices and for arria ii gz devices at a data rate less than 1.25 gbps 0.1 p-p b a u d/1667 20,000,000 jitter fre qu ency (hz) sin u soidal jitter amplit u de (ui) 20d b /dec 1?68 chapter 1: device datasheet for arria ii devices switching characteristics arria ii device handbook volume 3: device datasheet and addendum july 2012 altera corporation figure 1?6 shows the lvds soft-cdr/dpa sinusoidal jitter tolerance specification for arria ii gz devices at 1.25 gbps data rate. table 1?56 lists the lvds soft-cdr/dpa sinusoidal jitter tolerance specification for arria ii gz devices at 1.25 gbps data rate. external memory interface specifications f for the maximum clock rate supported for a rria ii gx and gz device family, refer to the external memory interface spec estimator page on the altera website. table 1?57 lists the external memory interface specifications for arria ii gx devices. figure 1?6. lvds soft-cdr/dpa sinusoidal jitter tolerance specifi cation for arria ii gz devices at a 1.25 gbps data rate jitter fre qu ency (hz) sin u soidal jitter amplit u de (ui) 25 8.5 0.35 0.1 10,000 (f1) 17,565 (f2) 1,493,000 (f3) 50,000,000 (f4) table 1?56. lvds soft-cdr/dpa sinusoidal jitter mask values for arria ii gz devices at 1.25 gbps data rate jitter frequency (hz) sinusoidal jitter (ui) f1 10,000 25.000 f2 17,565 25.000 f3 1,493,000 0.350 f4 50,000,000 0.350 table 1?57. external memory interface specifications for arria ii gx devices (part 1 of 2) frequency mode frequency range (mhz) resolution () dqs delay buffer mode (1) number of delay chains c4 i3, c5, i5 c6 0 90-140 90-130 90-110 22.5 low 16 1 110-180 110-170 110-150 30 low 12 2 140-220 140-210 140-180 36 low 10 3 170-270 170-260 170-220 45 low 8 4 220-340 220-310 220-270 30 high 12 chapter 1: device datasheet for arria ii devices 1?69 switching characteristics july 2012 altera corporation arria ii device han dbook volume 3: device datasheet and addendum table 1?58 lists the dll frequency range specif ications for arria ii gz devices. table 1?59 lists the dqs phase offset delay per stage for arria ii gx devices. 5 270-410 270-380 270-320 36 high 10 6 320-450 320-410 320-370 45 high 8 note to table 1?57 : (1) low indicates a 6-bit dqs delay setting; high indicates a 5-bit dqs delay setting. table 1?57. external memory interface specifications for arria ii gx devices (part 2 of 2) frequency mode frequency range (mhz) resolution () dqs delay buffer mode (1) number of delay chains c4 i3, c5, i5 c6 table 1?58. dll frequency range specifications for arria ii gz devices frequency mode frequency range (mhz) available phase shift dqs delay buffer mode (1) number of delay chains ?3 ?4 0 90-130 90-120 22.5, 45, 67.5, 90 low 16 1 120-170 120-160 30, 60, 90, 120 low 12 2 150-210 150-200 36, 72, 108, 144 low 10 3 180-260 180-240 45, 90,135, 180 low 8 4 240-320 240-290 30, 60, 90, 120 high 12 5 290-380 290-360 36, 72, 108, 144 high 10 6 360-450 360-450 45, 90, 135, 180 high 8 7 470-630 470-590 60, 120, 180, 240 high 6 note to table 1?58 : (1) low indicates a 6-bit dqs delay setting; high indicates a 5-bit dqs delay setting. table 1?59. dqs phase offset delay per setting for arria ii gx devices (note 1) , (2) , (3) speed grade min max unit c4 7.0 13.0 ps i3, c5, i5 7.0 15.0 ps c6 8.5 18.0 ps notes to table 1?59 : (1) the valid settings for phase offset ar e -64 to +63 for frequency modes 0 to 3 and -32 to +31 for frequency modes 4 to 5. (2) the typical value equals the averag e of the minimum and maximum values. (3) the delay settings are linear. 1?70 chapter 1: device datasheet for arria ii devices switching characteristics arria ii device handbook volume 3: device datasheet and addendum july 2012 altera corporation table 1?60 lists the dqs phase shift error for arria ii gx devices. table 1?61 lists the dqs phase shift error for arria ii gz devices. table 1?62 lists the memory output clock jitter specifications for arria ii gx devices. table 1?60. dqs phase shift error specification for dll-delayed clock (t dqs_pserr ) for arria ii gx devices (note 1) number of dqs delay buffer c4 i3, c5, i5 c6 unit 1 263036ps 2 526072ps 3 78 90 108 ps 4 104 120 144 ps note to table 1?60 : (1) this error specificat ion is the absolute maximum and minimum error. for exam ple, skew on three dqs delay buffers in a c4 speed grade is 78 ps or 39 ps. table 1?61. dqs phase shift error specification for dll-delayed clock (t dqs_pserr ) for arria ii gz devices (note 1) number of dqs delay buffer ?3 ?4 unit 12830ps 25660ps 38490ps 4 112 120 ps note to table 1?61 : (1) this error specificat ion is the absolute maximum and minimum error. for exam ple, skew on three dqs delay buffers in a 3 speed grade is 84 ps or 42 ps. table 1?62. memory output clock jitter specification for arria ii gx devices (note 1) , (2) , (3) parameter clock network symbol ?4 ?5 ?6 unit min max min max min max clock period jitter global t jit(per) -100 100 -125 125 -125 125 ps cycle-to-cycle period jitter global t jit(cc) -200 200 -250 250 -250 250 ps duty cycle jitter global t jit(duty) -100 100 -125 125 -125 125 ps notes to table 1?62 : (1) the memory output clock jitt er measurements are for 200 consecu tive clock cycles, as specifie d in the jedec ddr2/ddr3 sdram standard. (2) the clock jitter specification ap plies to memory output clock pins generated us ing ddio circuits clocked by a pll output rou ted on a global clock network. (3) the memory output clock jitter stated in table 1?62 is applicable when an inpu t jitter of 30 ps is applied. chapter 1: device datasheet for arria ii devices 1?71 switching characteristics july 2012 altera corporation arria ii device han dbook volume 3: device datasheet and addendum table 1?63 lists the memory output clock jitter specifications for arria ii gz devices. duty cycle distorti on (dcd) specifications table 1?64 lists the worst-case dcd specifications for arria ii gx devices. table 1?65 lists the worst-case dcd specifications for arria ii gz devices. table 1?63. memory output clock jitter specification for arria ii gz devices (note 1) , (2) , (3) parameter clock network symbol ?3 ?4 unit min max min max clock period jitter regional t jit(per) -55 55 -55 55 ps cycle-to-cycle period jitter regional t jit(cc) -110 110 -110 110 ps duty cycle jitter regional t jit(duty) -82.5 82.5 -82.5 82.5 ps clock period jitter global t jit(per) -82.5 82.5 -82.5 82.5 ps cycle-to-cycle period jitter global t jit(cc) -165 165 -165 165 ps duty cycle jitter global t jit(duty) -90 90 -90 90 ps notes to table 1?63 : (1) the memory output clock jitter measure ments are for 200 consecutive clock cycles, as specified in the je dec ddr2/ddr3 sdram standard. (2) the clock jitter specification ap plies to memory output clock pins generated using differential signa l-splitter and ddio cir cuits clocked by a pll output routed on a regional or globa l clock network as specified. altera reco mmends using regional clock networks whenever possible. (3) the memory output clock jitter stated in table 1?63 is applicable when an inpu t jitter of 30 ps is applied. table 1?64. duty cycle distortion on i/o pins for arria ii gx devices (note 1) symbol c4 i3, c5, i5 c6 unit min max min max min max output duty cycle 45 55 45 55 45 55 % note to table 1?64 : (1) the dcd specification ap plies to clock outputs from th e pll, global clock tree, ioe driving dedicated, and general purpose i/o pins. table 1?65. duty cycle distortion on i/o pins for arria ii gz devices (note 1) symbol c3, i3 c4, i4 unit min max min max output duty cycle 45 55 45 55 % note to table 1?65 : (1) the dcd specification applies to clo ck outputs from the pll, global clock tr ee, ioe driving dedicated, and general purpose i/o pins. 1?72 chapter 1: device datasheet for arria ii devices switching characteristics arria ii device handbook volume 3: device datasheet and addendum july 2012 altera corporation ioe programmable delay table 1?66 lists the delay associated with ea ch supported ioe programmable delay chain for arria ii gx devices. table 1?67 lists the ioe programmable delay settings for arria ii gz devices. table 1?66. ioe programmable delay for arria ii gx devices parameter available settings (1) minimum offset (2) maximum offset unit fast model slow model i3 c4 i5 i3 c4 c5 i5 c6 output enable pin delay 7 0 0.413 0.442 0.413 0.814 0.713 0.796 0.801 0.873 ns delay from output register to output pin 7 0 0.339 0.362 0.339 0.671 0.585 0.654 0.661 0.722 ns input delay from pin to internal cell 52 0 1.494 1.607 1.494 2.895 2.520 2.733 2.775 2.944 ns input delay from pin to input register 52 0 1.493 1.607 1.493 2.896 2.503 2.732 2.774 2.944 ns dqs bus to input register delay 4 0 0.074 0.076 0.074 0.140 0.124 0.147 0.147 0.167 ns notes to table 1?66 : (1) the available setting for every delay chai n starts with zero and en ds with the speci fied maximum number of settings. (2) the minimum offset represented in th e table does not include intrinsic delay. table 1?67. ioe programmable delay for arria ii gz devices parameter available settings (1) minimum offset (2) maximum offset unit fast model slow model industrial commercial c3 i3 c4 i4 d1 15 0 0.462 0.505 0.795 0.801 0.857 0.864 ns d2 7 0 0.234 0.232 0.372 0.371 0.407 0.405 ns d3 7 0 1.700 1.769 2.927 2.948 3.157 3.178 ns d4 15 0 0.508 0.554 0.882 0.889 0.952 0.959 ns d5 15 0 0.472 0.500 0.799 0.817 0.875 0.882 ns d6 6 0 0.186 0.195 0.319 0.321 0.345 0.347 ns notes to table 1?67 : (1) you can set this value in th e quartus ii software by selecting d1 , d2 , d3 , d4 , d5 , and d6 in the assignment name column. (2) minimum offset does not include the intrinsic delay. chapter 1: device datasheet for arria ii devices 1?73 i/o timing july 2012 altera corporation arria ii device han dbook volume 3: device datasheet and addendum i/o timing altera offers two ways to determine i/o timing: using the microsoft excel-based i/o timing. using the quartus ii timing analyzer. the microsoft excel-based i/o timing prov ides pin timing performance for each device density and speed grade. the data is typically used prior to designing the fpga to get an estimate of the timing budget as part of the link timing analysis. the quartus ii timing analyzer provides a more accurate and precise i/o timing data based on the specifics of the design after place-and-route is complete. f the microsoft excel-based i/o timing spreadsheet is downloadable from the literature: arria ii devices web page. 1?74 chapter 1: device datasheet for arria ii devices glossary arria ii device handbook volume 3: device datasheet and addendum july 2012 altera corporation glossary table 1?68 lists the glossary for this chapter. table 1?68. glossary (part 1 of 4) letter subject definitions a, b, c, d differential i/o standards receiver input waveforms transmitter output waveforms e, f f hsclk left/right pll input clock frequency. f hsdr high-speed i/o block: maximum/minimum lvds data transfer rate (f hsdr = 1/tui), non-dpa. f hsdrdpa high-speed i/o block: maximum/minimum lvds data transfer rate (f hsdrdpa = 1/tui), dpa. single-ended waveform differential waveform positive channel (p) = v ih negative channel (n) = v il ground v id v id v id p ? n = 0 v v cm single-ended waveform differential waveform positive channel (p) = v oh negative channel (n) = v ol ground v od v od v od p ? n = 0 v v cm chapter 1: device datasheet for arria ii devices 1?75 glossary july 2012 altera corporation arria ii device han dbook volume 3: device datasheet and addendum g, h, i, j j high-speed i/o block: deserialization factor (width of parallel data bus). jtag timing specifications jtag timing specifications: k, l, m, n, o, p pll specifications pll specification parameters: diagram of pll specifications (1) notes: (1) coreclock can only be fed by dedica ted clock input pins or pll outputs. (2) this is the vco post-scale counter k. q, r r l receiver differential input discrete resistor (external to the arria ii device). table 1?68. glossary (part 2 of 4) letter subject definitions tdo tck t jpzx t jpco t jph t jpxz t jcp t jpsu t jcl t jch tdi tms core clock external feedback reconfigurable in user mode key clk n m /k pfd switchover vco cp lf clkout pins gclk rclk f inpfd f in f vco f out f out_ext k (2) counters c0..c9 1?76 chapter 1: device datasheet for arria ii devices glossary arria ii device handbook volume 3: device datasheet and addendum july 2012 altera corporation s sw (sampling window) the period of time during which the data must be valid in order to capture it correctly. the setup and hold times determine the ideal strobe position within the sampling window: timing diagram single-ended voltage referenced i/o standard the jedec standard for sstl and hstl i/o standards define both the ac and dc input signal values. the ac values indicate the voltage levels at which the receiver must meet its timing specifications. the dc values indicate the voltage levels at which the final logic state of the receiver is unambiguously defined. after the recei ver input has crossed the ac value, the receiver changes to the new logic state. the new logic state is then maintained as long as the input stays beyond the ac threshold. this approach is intended to provide predictable receiver timing in the presence of input waveform ringing: single-ended voltage referenced i/o standard t t c high-speed receiver and transmitter input and output clock period. tccs (channel-to- channel- skew) the timing difference between the fastest and slowest output edges, including t co variation and clock skew, across channels driven by the sa me pll. the clock is included in the tccs measurement (refer to the timing diagram figure under s in this table). t duty high-speed i/o block: duty cycle on the high-speed transmitter output clock. timing unit interval (tui) the timing budget allowed for skew, propagation delays, and data sampling window. (tui = 1/(receiver input clock frequency multiplication factor) = t c / w ) t fall signal high-to-low transition time (80-20%) t inccj cycle-to-cycle jitter tolerance on the pll clock input. t outpj_io period jitter on the general purpose i/o driven by a pll. t outpj_dc period jitter on the dedicated clock output driven by a pll. t rise signal low-to-high transition time (20-80%). table 1?68. glossary (part 3 of 4) letter subject definitions bit time 0.5 x tccs rskm sampling window (sw) rskm 0.5 x tccs v ih ( ac ) v ih(dc) v ref v il(dc) v il(ac ) v oh v ol v ccio v ss chapter 1: device datasheet for arria ii devices 1?77 document revision history july 2012 altera corporation arria ii device han dbook volume 3: device datasheet and addendum document revision history table 1?69 lists the revision history for this chapter. u, v v cm(dc) dc common mode input voltage. v icm input common mode voltage: the common mode of the differential signal at the receiver. v id input differential voltage swing: the difference in voltage between the positive and complementary conductors of a differential transmission at the receiver. v dif(ac) ac differential input voltage: minimum ac input differential voltage required for switching. v dif(dc) dc differential input voltage: minimum dc input differential voltage required for switching. v ih voltage input high: the minimum positive voltage applied to the input which is accepted by the device as a logic high. v ih(ac) high-level ac input voltage. v ih(dc) high-level dc input voltage. v il voltage input low: the maximum positive voltage applied to the input which is accepted by the device as a logic low. v il(ac) low-level ac input voltage. v il(dc) low-level dc input voltage. v ocm output common mode voltage: the common mode of the differential signal at the transmitter. v od output differential voltage swing: the difference in voltage between the positive and complementary conductors of a differential transmission at the transmitter. w, x, y, z w high-speed i/o block: the clock boost factor. table 1?68. glossary (part 4 of 4) letter subject definitions table 1?69. document revision history (part 1 of 2) date version changes july 2012 4.3 updated the v cch_gxbl/r operating conditions in table 1?6 . finalized arria ii gz information in table 1?20 . added blvds specification in table 1?32 and table 1?33 . updated input and output waveforms in table 1?68 . december 2011 4.2 updated table 1?32, table 1?33, table 1?34, table 1?35, table 1?40, table 1?41, table 1?54, and table 1?67. minor text edits. june 2011 4.1 added table 1?60. updated table 1?32, table 1?33, table 1?38, table 1?41, and table 1?61. updated the ?switching characteristics? section introduction. minor text edits. 1?78 chapter 1: device datasheet for arria ii devices document revision history arria ii device handbook volume 3: device datasheet and addendum july 2012 altera corporation december 2010 4.0 added arria ii gz information. added table 1?61 with arria ii gx information. updated table 1?1, table 1?2, table 1?5, ta ble 1?6, table 1?7, table 1?11, table 1?35, table 1?37, table 1?40, table 1?42, table 1?44, table 1?45, table 1?57, table 1?61, and table 1?63. updated figure 1?5. updated for the quartus ii version 10.0 release. updated the first paragraph for searchability. minor text edits. july 2010 3.0 updated table 1?1, table 1?4, table 1?16, table 1?19, table 1?21, table 1?23, table 1?25, table 1?26, table 1?30, and table 1?35 added table 1?27 and table 1?29. added i3 speed grade information to table 1?19, table 1?21, table 1?22, table 1?24, table 1?25, table 1?30, table 1?32, table 1?33, table 1?34, and table 1?35. updated the ?operating conditions? section. removed ?preliminary? from table 1?19, table 1?21, table 1?22, table 1?23, table 1?24, table 1?25, table 1?26, table 1?28, table 1?30, table 1?32, table 1?33, table 1?34, and figure 1?4. minor text edits. march 2010 2.3 updated for the quartus ii version 9.1 sp2 release: updated table 1?3, table 1?7, table 1?19, table 1?21, table 1?22, table 1?24, table 1?25 and table 1?33. updated ?recommended operating conditions? section. minor text edits. february 2010 2.2 updated table 1?19. february 2010 2.1 updated for arria ii gx v9.1 sp1 release: updated table 1?19, table 1?23, table 1?28, table 1?30, and table 1?33. added figure 1?5. minor text edits. november 2009 2.0 updated for arria ii gx v9.1 release: updated table 1?1, table 1?4, table 1?13, table 1?14, table 1?19, table 1?15, table 1?22, table 1?24, and table 1?28. added table 1?6 and table 1?33. added ?bus hold? on page 1?5. added ?ioe programmable delay? section. minor text edit. june 2009 1.2 updated table 1?1, table 1?3, table 1?7, ta ble 1?8, table 1?18, table 1?23, table 1?25, table 1?26, table 1?29, table 1?30, table 1?31, table 1?32, and table 1?33. added table 1?32. updated equation 1?1. march 2009 1.1 added ?i/o timing? section. february 2009 1.0 initial release. table 1?69. document revision history (part 2 of 2) date version changes arria ii device handbook volume 3: device datasheet and addendum december 2010 aiigx53002-2.0 subscribe ? 2010 altera corporation. all rights reserved. altera, arria, cy clone, hardcopy, max, megacore , nios, quartus and stratix are reg. u.s. pat. & tm. off. and/or trademarks of altera corporation in the u.s. and other countries. all other trademarks and service marks are the propert y of their respective holders as described at www.altera.com/common/legal.html . altera warrants performance of its semiconductor products to cu rrent specifications in accordan ce with altera?s standard warr anty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability arising out of th e application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. alte ra customers are advi sed to obtain the latest version of device specifications before relying on any published information and before placi ng orders for products or services. 2. addendum for the arria ii device handbook this chapter describes changes to the published version of the arria ii device handbook. all changes from revision 1.1 of this chapter are now incorporated in the main handbook chapters. highlights f this information is now located in the overview for the arria ii device family chapter. high-speed lvds i/o wi th dpa and soft cdr f this information is now located in the overview for the arria ii device family chapter. auto-calibrating external memory interfaces f this information is now located in the overview for the arria ii device family chapter. connecting a serial configuration de vice to an arria ii device family on as interface f this information is now located in the configuration, design security, and remote system upgrades in arria ii devices chapter. document revision history table 2?1 lists the revision history for this chapter. table 2?1. document revision history date version changes december 2010 2.0 updated chapter titles. july 2010 1.2 moved the ?highlights?, ?high-speed lvds i/o with dpa and soft cdr?, and ?auto-calibrating external memory interfaces? sections to the arria ii gx device family overview chapter. moved the ?guidelines for connecting serial configuration device to arria ii gx device family on as interface? section to the configuration, design security, and remote system upgrades in arria ii gx devices chapter march 2010 1.1 added ?guidelines for connecting serial configuration device to arria ii gx device family on as interface? february 2010 1.0 initial release. december 2010 aiigx53002-2.0 2?2 chapter 2: addendum for the arria ii device handbook document revision history arria ii device handbook volume 3: device datasheet and addendu m december 2010 altera corporation july 2012 altera corporation arria ii device han dbook volume 3: device datasheet and addendum additional information this chapter provides additional informat ion about the arria ii device handbook and altera. about this handbook this handbook provides comprehensive information about the altera ? arria ii gx family of devices. how to contact altera to locate the most up-to-date informat ion about altera products, refer to the following table. typographic conventions the following table shows the typographic conventions this document uses. contact (1) contact method address technical support website www.altera.com/support technical training website www.altera.com/training email custrain@altera.com product literature website www.altera.com/literature non-technical support (general) email nacomp@altera.com (software licensing) email authorization@altera.com note to table: (1) you can also contact yo ur local altera sales office or sales representative. visual cue meaning bold type with initial capital letters indicate command names, dialog box titles, dialog box options, and other gui labels. for example, save as dialog box. for gui elements, capitalization matches the gui. bold type indicates directory names, project names, di sk drive names, file names, file name extensions, software utility names, and gui labels. for example, \qdesigns directory, d: drive, and chiptrip.gdf file. italic type with initial capital letters indicate document titles. for example, stratix iv design guidelines . italic type indicates variables. for example, n + 1. variable names are enclosed in angle brackets (< >). for example, info?2 additional information typographic conventions arria ii device handbook volume 3: device datasheet and addendum july 2012 altera corporation courier type indicates signal, port, register, bit, block, and primitive names. for example, data1 , tdi , and input . the suffix n denotes an active-low signal. for example, resetn . indicates command line commands and anything that must be typed exactly as it appears. for example, c:\qdesigns\tutorial\chiptrip.gdf . also indicates sections of an actual file, such as a report file, references to parts of files (for example, the ahdl keyword subdesign ), and logic function names (for example, tri ). r an angled arrow instructs you to press the enter key. 1., 2., 3., and a., b., c., and so on numbered steps indicate a list of items when the sequence of the items is important, such as the steps listed in a procedure. bullets indicate a list of items when the sequence of the items is not important. 1 the hand points to information that requires special attention. h a question mark directs you to a software help system with related information. f the feet direct you to another document or website with related information. c a caution calls attention to a condition or possible situation that can damage or destroy the product or your work. w a warning calls attention to a condition or possible situation that can cause you injury. the envelope links to the email subscription management center page of the altera website, where you can sign up to receive update notifications for altera documents. visual cue meaning |
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